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december 1999 1 copyright ? 1999 by lsi logic corporation. all rights reserved. ? CWDSP1670 lead vehicle technical summary contents 1 introduction 5 2 functional overview 5 3 signal descriptions 7 3.1 d bus interface 9 3.2 external registers interface 10 3.3 interrupts interface 10 3.4 clocks 12 3.5 wait controls 12 3.6 user i/o interface 13 3.7 reset, abort, and boot 13 3.8 scanice interface 15 3.9 test interface 16 3.10 miscellaneous 17 4 registers 18 4.1 d bus interface registers (r1Cr3) 19 4.2 cgu register 21 4.3 mode id register 21 4.4 output port register 22 4.5 timer registers 22 5 memory organization 25 5.1 program memory 25 5.2 data memory 25 6 functional description 28 6.1 core overview 29 6.2 clock generator unit 32 6.3 d bus interface 32 6.4 timer 36 6.5 output port 36 6.6 external register interface 37
2 CWDSP1670 lead vehicle technical summary 6.7 interrupts 38 6.8 on-chip boot rom 38 6.9 scanice interface 40 7 sample boot program 40 8 speci?cations 63 8.1 electrical characteristics 63 8.2 ac timing 65 8.3 package pinout and mechanical drawing 70 9 known limitations 91 9.1 int3_vec pin 91 figures 1 CWDSP1670 lead vehicle block diagram 6 2 i/o signals 8 3 r1 register layout 19 4 r2 register layout 19 5 r3 register layout 20 6 cgu register layout 21 7 mode id register layout 22 8 output port register layout 22 9 timer reload register 23 10 timer control register layout 23 11 timer count registers 24 12 program memory map 25 13 data memory map 26 14 CWDSP1670 dsp core block diagram 30 15 d bus interface signals 33 16 d bus data read timing 34 17 d bus data write timing 34 18 d bus i/o read timing 35 19 d bus i/o write timing 35 20 external registers interface timing 37 21 lead vehicle boot flow 41 22 internal clocks 65 23 d bus read timing (1 wait state) 66 24 d bus write timing (1 wait state) 67 25 i/o space read timing (2 wait states) 68
CWDSP1670 lead vehicle technical summary 3 26 i/o space write timing (2 wait states) 69 27 225 pbga (ib) mechanical drawing 89 28 pin assignments seen from solder ball side 90 tables 1 lead vehicle registers 18 2 data memory allocation 27 3 boot mode selection 38 4 self-test status outputs 39 5 absolute maximum ratings 63 6 recommended operating conditions for 60 mhz maximum operating frequency 63 7 recommended operating conditions for 80 mhz maximum operating frequency 64 8 capacitance 64 9 dc characteristics 64 10 d bus read/write timing 67 11 i/o space read/write timing 69 12 alphabetical signal listing 70 13 signal listing by ball number 79
4 CWDSP1670 lead vehicle technical summary
CWDSP1670 lead vehicle technical summary 5 1 introduction the CWDSP1670 lead vehicle is an oakdspcore ? -based, application- speci?c integrated circuit (asic) that is used as a reference device for system and software development. the CWDSP1670 lead vehicle is more suitable to asic development than previous generations and includes basic peripheral functions that allow you, with additional hardware, to develop a prototype design. prototype software also can be debugged and benchmarked on the system. 2 functional overview figure 1 shows a functional block diagram of the lead vehicle. its main functional blocks are: CWDSP1670 dsp core 32 kwords of on-chip x ram 4 kwords of on-chip y ram 32 kwords of on-chip instruction ram (i ram) 1 kword of on-chip boot rom 31 kwords of on-chip program ram (p ram) 8 kwords of on-chip e ram clock generator unit mode id register timer d bus interface output port
6 CWDSP1670 lead vehicle technical summary figure 1 CWDSP1670 lead vehicle block diagram the CWDSP1670 core contains an integral scanice control unit and on-chip emulation module (ocem). refer to the CWDSP1670 dsp core technical manual for details on these core components. the core has three data bus interfaces (x, y, and e) and two instruction bus interfaces (i and p). it can address up to 64 kwords of data space and 64 kwords of instruction space. the external memory con?guration is e-bus mux ccu cwdsp x ram y ram x y p clock d bus generator e bus p bus dmem_clk pmem_clk internal main clock master clock core_clk on-chip boot rom wait timer interface gating off-chip wait request p-bus mux mem_cfg scanice boot select unit external register interface ext reg interface i ram p ram e ram output port mode id register (4k) (32k) (32k) (31k) (1k) (8 k) interrupts interrupt acknowledges interrupts interface control 1670 core e ocem i
CWDSP1670 lead vehicle technical summary 7 reported to the core on its mem_cfg inputs which are tied high or low appropriately in the lead vehicle. the clock generator unit derives the internal main clock from the master clock input and provides a register-controlled stop mode. the core e bus space is divided among e ram, the mode id register, the timer, the external d bus, and the output port. the mode id register lets you identify normal or data memory map compatibility (dmmc) memory mapping, two modes of allocating y ram and d bus space. the dmmc mode provides memory mapping compatibility with previous cwdsp16x0 lead vehicles. the dmmc_mode input to the lead vehicle selects the mapping mode (see section 3.10, miscellaneous ). the programmable timer can be used to generate a single or repeated interrupts on any one of the cores interrupt inputs (int0Cint3 or nmi). the timer can be halted and restarted or reset by the host on the d bus. the d bus interface connects an external, 16-bit address and 16-bit, bidirectional data bus to the core in the e bus address space. d bus wait states can be programmed into the interface. the output port provides eight user-de?ned output signals which can be used for bank switching when booting from d bus memories. the external register interface allows CWDSP1670 instructions to access four, user-de?ned, 16-bit, off-chip registers. the interface includes separate 16-bit input and output data buses, multiplexer controls for selecting one register during a read cycle, and read/write controls for the four registers. the boot select input lets an external host control the source of boot code. 3 signal descriptions this section provides detailed descriptions of CWDSP1670 lead vehicle signals. figure 2 shows all of the lead vehicles i/o signals organized by interface or function. note: signals that are low when active have an _n suf?x. sig- nals that are high when active do not have the suf?x.
8 CWDSP1670 lead vehicle technical summary figure 2 i/o signals da[15:0] dd[15:0] dc_n dr_n dw_n d_dma_n ioc_n ior_n iow_n d bus interface xrdi[15:0] xrdo[15:0] sel_xr_rd[1:0] xrw3 _n -0_n xrr3 _n -0_n external registers interface ext_scan_in ext_scan_out ext_scan_ctl ext_scan_alert ext_scan_clk ext_scan_rst scan_debug_en scanice_mode mclk oak_clk clk_ug clkout_en clocks wait_ctl_n emem_wait edb_wait_en wait control rst_n abort_n mp_reset mp_abort mp_boot rst_out_n abort_out reset, abort, & boot nmi_n iack_nmi_n int3_n-0_n iack_int3_n-0_n im3 int3_cntx_en int3_vec[15:0] boot_n self_test_n brrm1 level_int_mode scanice interface iiddtn tn procout ptst ptst_te iu[1:0] ou[1:0] outp[7:0] user i/o test interface CWDSP1670 lead vehicle pprotect_en dmmc_mode ocem_susp stop_mode d_dma_grant vss vdd2 core vdd4 miscellaneous interrupts interface timer_clk escan_out escan_en escan_in vdd2 lv
CWDSP1670 lead vehicle technical summary 9 3.1 d bus interface da[15:0] d bus address output data and i/o space address bus. the data and i/o space allocation is shown in the following table. dd[15:0] d bus data bidirectional data and i/o space data bus. dc_n d bus data space chip select output data space device select signal. this signal is asserted when the d bus address is in the data space range. dr_n d bus read enable output data space read enable signal. this signal is asserted when the d bus address is in the data space range and the lead vehicle requests a read from data space. dw_n d bus write enable output data space write enable signal. this signal is asserted when the d bus address is in the data space range and the lead vehicle wishes to write to data space. d_dma_n dma request input this signal is asserted by an external dma controller to request control of the d bus. d_dma_grant d bus dma grant output the lead vehicle asserts this signal to grant control of the d bus to the external dma controller. ioc_n d bus i/o space chip select output i/o chip select output signal. this signal is asserted when the d bus address is in the i/o space range. normal mode dmmc mode space range size (words) range size (words) data 0x8000C 0xbfff 16 k 0x8000C 0xbfff 16 k 0xe000C 0xe7ff 2 k 0xe000C 0xefff 4k i/o 0xe800C 0xebff 1 k 0xf000C 0xf3ff 1k
10 CWDSP1670 lead vehicle technical summary ior_n d bus i/o space read enable output i/o read enable output signal. this signal is asserted when the d bus address is in the i/o space range and the lead vehicle requests a read from i/o space. iow_n d bus i/o space write enable output i/o write enable output signal. this signal is asserted when the d bus address is in the i/o space range and the lead vehicle wishes to write to i/o space. 3.2 external registers interface xrdi[15:0] external register data input bus input data bus from the selected external register to the lead vehicle. xrdo[15:0] external register data output bus output data bus from lead vehicle to the selected external reg- ister. sel_xr_rd[1:0] external register read select output these signals allow the multiplexing of the read data from the external registers onto the xrdi[15:0] input data bus. xrw3_n, xrw2_n, xrw1_n, xrw0_n external registers write enables outputs write enables for external registers 3C0. xrr3_n, xrr2_n, xrr1_n, xrr0_n external registers read enables outputs read enables for external registers 3C0. 3.3 interrupts interface nmi_n nonmaskable interrupt input when this signal is asserted, the CWDSP1670 core in the lead vehicle calls the nmi service routine at vector address 0x0004. this interrupt cannot be internally masked by software. nmi_n is internally synchronized with the rising edge of the mclk input clock. iack_nmi_n nonmaskable interrupt acknowledge output the CWDSP1670 core asserts this signal to acknowl- edge receipt of the nmi_n interrupt.
CWDSP1670 lead vehicle technical summary 11 int2_n, int1_n, int0_n interrupts 0C2 inputs when any of these signals are asserted, the CWDSP1670 core calls the interrupt service routine at vector address 0x0016 for int2_n, 0x000e for int1_n, or 0x0006 for int0_n. the interrupts can be internally masked by software. the interrupt input signals are inter- nally synchronized with the rising edge of the mclk input clock. int3_n externally vectored interrupt input when this signal is asserted and not masked by the im3 input, the CWDSP1670 core calls the service routine at the vector address speci?ed by the int3_vec[15:0] input. int3_n is internally synchronized with the rising edge of the mclk input clock. iack_int2_n, iack_int1_n, iack_int0_n acknowledge interrupts 2 to 0 outputs the CWDSP1670 core asserts these signals to acknowl- edge branching to the service routine for the correspond- ing interrupt. iack_int3_n acknowledge interrupt 3 output the cwdsp core asserts this signal to acknowledge branching to the service routine for interrupt 3. im3 int3_n mask input when this signal is asserted, the int3_n interrupt input is masked from the core processor. int3_cntx_en int3_n context switching enable input tie this pin high for automatic context switching when an int3_n interrupt occurs. int3_vec[15:0] int3_n vector input this 16-bit input is used to specify the address of the ser- vice routine for the int3_n input interrupt. pins 0 and 1 must be tied to vss. see section 9, known limitations for further hints.
12 CWDSP1670 lead vehicle technical summary level_int_mode level triggered interrupt mode select input this signal must be tied low for edge-triggered interrupt mode or tied high for level-triggered interrupt mode. 3.4 clocks mclk master clock input all chip internal and output clocks are derived from mclk. oak_clk oak clock output wait-stated copy of mclk input skewed to align with the internal chip clock. clk_ug ungated clock output non-wait-stated copy of mclk input skewed to align with the internal chip clock to be used by the d bus interface. clkout_en clock out enable input when asserted, enables all output clocks; oak_clk, clk_ug, and timer_clk. timer_clk timer clock output mclk input to the timer gated by clkout_en. 3.5 wait controls wait_ctl_n core clock wait states control input while this signal is asserted, wait states are inserted into the CWDSP1670 cores pmem_clk and core_clk. emem_wait e memory wait state input when this signal is asserted at reset, the m6 bit in the r3 register is cleared and there are no block 6 e memory wait states. when this signal is deasserted at reset, the m6 bit is set and the number of block 6 e memory wait states is determined by the setting of the w6 ?eld in the r1 register (1 to 16 wait states). the m6 bit can also be set by software. edb_wait_en e bus automatic wait state enable input when this signal is asserted, e memory accesses have an automatic, single, wait state.
CWDSP1670 lead vehicle technical summary 13 3.6 user i/o interface iu[1:0] user input input these two signals are the CWDSP1670 core general pur- pose inputs. their states are written to bits 10 and 11 of core status register 2. ou[1:0] user output output these two control signals are the general purpose out- puts of the CWDSP1670 lead vehicle and re?ect bits 9 and 8 of status register 2. these signals are deasserted at reset. after self-test boot, the self-test status is indi- cated on these two signals as in the following table: outp[7:0] user output port output these signals re?ect the states of bits [7:0] of the output port register. see output port register description. 3.7 reset, abort, and boot rst_n reset input asserting this signal resets the core and clears all of its registers. rst_n must be held asserted for at least six mclk cycles. after the core terminates the reset period, program execution restarts at program address 0x0000. abort_n abort input initiates a breakpoint, allowing the debugger to regain control and halt core code execution. boot_n and self_test_n inputs the on-chip boot rom provides three different modes of boot operation, self-test boot, boot from d bus, and nor- mal boot, under control of the boot_n and self_test_n signals per the following table. the status ou[1:0] status 0b00 all tests pass 0b01 data memory failure(s) 0b10 program memory or rom failure(s) 0b11 other failure(s)
14 CWDSP1670 lead vehicle technical summary of self_test_n can be read from the d bus interface registers (see the stb bit on page 20 ). brrm1 branch to self indication output brrm1 is asserted when the core executes a brr -l instruction, indicating an in?nite loop at a single address. this indication can hence be used to determine when the end of a program has been reached or when the boot code branched to self. mp_reset external host reset input when this signal is asserted by an external host, the core is fully reset. mp_reset must be held asserted for at least six clk_ug (mclk with no wait states) cycles. after the core terminates the reset period, program exe- cution restarts at program address 0x0000 and the core boots. (see also mp_boot.) mp_reset can be masked by the mprc bit in the scanice control register. mp_abort external host abort input when this signal is asserted, it forces a breakpoint in the program and causes the core to go into the debug mode. mp_abort can be masked by the mpac bit in the scanice control register. mp_boot external host boot input mp_boot can be asserted by an external host when the host deasserts mp_reset to force the core to boot from the internal boot rom. mp_boot has identical function- ality to boot_n including the combination with boot_n self_test_n boot operation 0 0 self-test boot. CWDSP1670 executes self test code in rom during boot. see ou[1:0] signals. 0 1 d bus boot. CWDSP1670 executes d bus boot loading data from device located at the base of block 4 (0x8000) in d bus data memory space. 1 x normal boot. CWDSP1670 executes code from address 0x0000.
CWDSP1670 lead vehicle technical summary 15 self_test_n for different boot modes. mp_boot can be masked by the mpbc bit in the scanice control reg- ister. rst_out_n chip reset indicator output rst_out_n is asserted when: the rst_n input signal is asserted, the ext_scan_rst input signal is asserted, the rst bit in the scanice control register is set, or the mp_reset input signal is asserted and not masked by the mprc bit in the scanice control reg- ister. abort_out chip abort indicator output this signal is asserted to indicate the on-chip emulation module (ocem) raised a breakpoint interrupt and put the core in debug mode. 3.8 scanice interface the ?rst six signals listed below are compatible with existing oakdspcore debugging systems. the last two signals (scan_debug_en and scanice_mode) are additional scanice monitor and control signals that can be incorporated in your design. ext_scan_in external scan in input serial scan test data in to the core scanice unit from an external control system. ext_scan_out external scan out output serial scan test data out from the core scanice unit to an external control system. ext_scan_ctl external scan control input when asserted, triggers the core scanice control regis- ter loading protocol.
16 CWDSP1670 lead vehicle technical summary ext_scan_alert external scan alert output this signal is asserted when the core is in scanice mode. it is used to alert the external control system that this state has been entered. ext_scan_clk external scan clock input external scan clock input to core. ext_scan_rst external scan reset input core reset input from the external control system. scan_debug_en scanice debug enable input asserting this signal enables scanice debug. note: the debugger cannot be used unless this signal is asserted. scanice_mode scanice mode indicator output when asserted, indicates that scanice debug mode is active. 3.9 test interface the signals listed in this section are for the lsi logic production testing only. for normal operation, connect them or leave them unconnected as indicated. iiddtn production test input tie this pin low for normal operation. tn production test input tie this pin low for normal operation. procout process monitor indicator output leave this pin unconnected. ptst production test enable input tie this pin low for normal operation. ptst_te production test scan chain load enable input tie this pin low for normal operation.
CWDSP1670 lead vehicle technical summary 17 escan_out reserved output leave this pin unconnected. escan_en reserved input tie this pin low for normal operation. escan_in reserved input tie this pin low for normal operation. 3.10 miscellaneous pprotect_en program protection enable input a typical method for attempting to read program memory is to copy the data in it to data memory using the movp instruction in code running from off-chip memory. when the pprotect_en pin is tied high, any attempt to read data from the i bus using the movp instruction (execut- ing from p bus space) results in garbage being read, thus preventing this data from being copied into data memory. note: this signal does not serve a useful purpose on the lead vehicle but is provided to demonstrate operation of this core feature. dmmc_mode input when asserted, the lead vehicle is memory mapped in the dmmc mode. when deasserted, normal memory mapping is used. see section 5.2, data memory. ocem_susp ocem suspend input asserting this signal disables the clocks within the ocem, thus effectively reducing the power consumed by this module to zero. see the suspend signal descrip- tion in the CWDSP1670 dsp core technical manual. note: the debugger cannot be used unless this signal is asserted. stop_mode core stop mode indicator output when asserted, indicates that the CWDSP1670 core is in the stop mode, that is, the core clocks are stopped. vdd2 core CWDSP1670 core power input +2.5 v to core.
18 CWDSP1670 lead vehicle technical summary vdd2 lv lead vehicle power input +2.5 v to lead vehicle components external to the core. vdd4 power input +3.3 v to i/o buffers of lead vehicle. vss ground bidirectional 4 registers this section describes the registers in the lead vehicle external to the CWDSP1670 dsp core. refer to the CWDSP1670 dsp core technical manual for descriptions of the cores registers. all of the lead vehicle registers are located in the top 1 kword of the d bus memory space. the registers have two addresses, one each for the normal and dmmc memory modes. the registers and their addresses are listed in ta b l e 1 . table 1 lead vehicle registers register dmmc mode address normal mode address function r0 0xf7e0 0xec00 blank, provided for backward compatibility with pre- vious lead vehicles. r1 0xf7e1 0xec01 sets number of d bus access wait states. r2 0xf7e2 0xec02 set number of i/o access wait states. r3 0xf7e3 0xec03 enable/disable e ram wait states. cgu 0xf7e4 0xec04 stop mode enable/disable and interrupt select for recovery. mode id 0xf7e6 0xec06 holds base address of d bus memory space output port 0xf7e7 0xec07 user output bits re?ected on outp[7:0] output pins. timer reload value 0xf7e8 0xec08 timer starts at this value and counts down to zero. timer control 0xf7e9 0xec09 controls timer speed, mode, and interrupt status. timer count 0xf7ea 0xec0a holds the timers current count. timer count 0xf7eb 0xec0b holds the timers current count.
CWDSP1670 lead vehicle technical summary 19 note: the register bits and ?elds labeled reserved are non- functional. although the descriptions for them tell you to clear them when writing to the registers, writing ones to them will not affect the operation of the lead vehicle. 4.1 d bus interface registers (r1Cr3) this section shows the layout of the r1 through r3 registers (see figures 3 through 5) and describes their bits and ?elds. see ta b l e 1 for register addresses. figure 3 r1 register layout the four ?elds in this register set the number of wait states for memory blocks 4 (w4 ?eld) through 7 (w7 ?eld). an entry of 0x0 causes one wait state, 0x1 causes two wait states, and so on. the w6 ?eld is effective only when the m6 bit in the r3 register is cleared. figure 4 r2 register layout the wio ?eld in this register sets the number of wait states for the d bus i/o space. an entry of 0x0 causes one wait state, 0x1 causes two wait states, and so on. 15 12 11 8 7 4 3 0 w7 w6 w5 w4 read/write status and default value: r/w 0xf 0x0 0xff 15 87 43 0 reserved w1o reserved read/write status and default value: r/w 0xf
20 CWDSP1670 lead vehicle technical summary note: for correct operation of i/o accesses, use a minimum of two wait states (wio = 0x1). figure 5 r3 register layout r reserved [3:0], [12:9], [15:14] clear these bits when writing to this register. m4, m5 4, 5 not used, provided for backward compatibility with previ- ous lead vehicles. m6 6 block 6 (0xc000C0xdfff) of e data memory is assigned to the on-chip e ram. when m6 is set, the number of wait states for e ram accesses is controlled by the w6 ?eld in the r1 register. when m6 is cleared, there are no wait states. m7 7 not used, provided for backward compatibility with previ- ous lead vehicles. cio 8 not used, provided for backward compatibility with previ- ous lead vehicles. stb self-test indicator 13 this bit is set when the self_test_n input signal is asserted and cleared when self_test_n is deas- serted. note . this bit is not registered, so any value written to it is ignored. 15 14 13 12 9 8 7 6 5 4 3 0 r stb r cio m7 m6 m5 m4 r read/write status and default value: r/w see descrip -tion 0x1f
CWDSP1670 lead vehicle technical summary 21 4.2 cgu register the clock generator unit register is shown in figure 6 and its bits are described following the ?gure. see ta b l e 1 for the registers addresses. figure 6 cgu register layout r reserved [6:0] clear these bits when writing to this register. s0, s1 clock stop [8:7] when either of these bits are set, the cgu in the lead vehicle interrupts the main clock to the CWDSP1670 core stopping all clocks in the core. i0Ci3 restart clock on interrupt [12:9] when one of these bits is set, the associated interrupt (int0Cint3) re-enables the core clocks. note: the nmi (nonmaskable interrupt) always restarts the core clocks when it occurs during stop mode. r reserved [15:13] clear these bits when writing to this register. 4.3 mode id register this register holds the base address of the d bus interface registers for the memory-mapped mode of the lead vehicle. when the dmmc_mode input to the lead vehicle is asserted, memory is mapped in the dmmc mode and this register holds address 0xf7e0. when dmmc_mode is deasserted for normal mode memory mapping, this register holds address 0xec00 (see figure 7). see ta b l e 1 for the addresses of this register. 15 131211109876 0 r i3i2i1i0s1s0 r read/write status and default value: r/w 0x00
22 CWDSP1670 lead vehicle technical summary figure 7 mode id register layout 4.4 output port register the output port register is shown in figure 8 . the states of the outp7C0 bits are re?ected on the outp[7:0] pins of the lead vehicle. you can use these bits and pins for such operations as bank switching when booting from d bus memories. the upper address bits for those memories can be written into this register. see ta b l e 1 for the registers addresses. note: the lead vehicle boot rom uses outp[1:0] for generation of additional address lines during a boot from the d bus. see section 6.5, output port. figure 8 output port register layout 4.5 timer registers the timer registers include the timer reload, timer control, and timer count registers. the ?gures in this section show their layouts, and their bits and ?elds are described in the paragraphs following figures 9 through 11. 15 0 d bus interface registers base address read only 15 876543210 r outp 7 outp 6 outp 5 outp 4 outp 3 outp 2 outp 1 outp 0 read/write status and default value: r/w 0x00
CWDSP1670 lead vehicle technical summary 23 figure 9 timer reload register the value written into this register is the value the lead vehicle timer returns to, after it counts down to zero, in periodic mode (see bit 1 in the timer control register). see ta b l e 1 for the addresses of this register. figure 10 timer control register layout timer enable 0 when this bit is set, the lead vehicle timer is enabled. when this bit is cleared the timer is stopped. this bit, with bit 9, can be used to stop and restart the timer at the stopped count or the reload value. periodic mode enable 1 when this bit is set, the timer operates continuously. it starts at the reload value in the timer reload register, counts down to zero, returns to the reload value and continues counting down again. when this bit is cleared, the timer starts at the reload value, counts down to zero, and stops. the timer enable bit is cleared at stop. setting the timer enable bit starts another single countdown. enable prescaler 1 2 when this bit is set, prescaler 1 divides the input clock to the timer by 16. the timer clock is a copy of mclk. 15 0 reload value r/w 15 14 10 9 8 7 6 5 4 3 2 1 0 stopped indicator r disable reload after stop enable nmi enable int3 enable int2 enable int1 enable int0 enable pre- scaler 2 enable pre- scaler 1 periodic mode enable timer enable read/write status: read only write only
24 CWDSP1670 lead vehicle technical summary enable prescaler 2 3 when this bit and bit 2 are set, prescaler 1 and 2 divide the input clock to the timer by a total of 256. prescaler 2 is not functional unless both bits are set. enable int0C3 [7:4] when any of these bits are set, the corresponding inter- rupt is asserted to the CWDSP1670 core when the timer count reaches zero. this feature is disabled when the bit is cleared. multiple interrupts can be enabled. enable nmi 8 when this bit is set, nmi is asserted to the CWDSP1670 core when the timer count reaches zero. this feature is disabled when the bit is cleared. nmi can be enabled in combination with any of the int0C3 interrupts. disable reload after stop 9 when this bit is set and the timer is stopped and restarted with bit 0, it restarts at the stopped count. when this bit is cleared, the timer restarts at the reload value. r reserved [14:10] clear this bit when writing to this register. stopped indicator 15 this bit is set when the timer is stopped and cleared when it is counting down. figure 11 timer count registers these two registers each contain the current count of the timer. 15 0 count value read only count value read only
CWDSP1670 lead vehicle technical summary 25 5 memory organization the CWDSP1670 core can address up to 64 kwords of program memory and 64 kwords of data memory. it contains x, y, and e data memory buses, and i and p program memory buses. 5.1 program memory as shown in figure 1 , 64 kwords of program memory are included in the lead vehicle as a 32 kword program ram on the i bus, a 1 kword boot rom and a 31 kword program ram on the p bus. figure 12 shows the memory map for these. figure 12 program memory map the d bus boot program and self-test boot program are located in zero wait-state, on-chip rom. see section 6.8.1, self-test boot. 5.2 data memory the lead vehicle contains 44 kwords of data memory con?gured as 32 kwords of x ram, 4 kwords of y ram, and 8 kwords of e ram. the remaining 20 kwords of data space are allocated to the cores e bus and 0xffff 0xfc00 0x8000 0x0000 0x7fff 0xfbff boot rom (1 kword) program ram, p bus (31 kwords) program ram, i bus (32 kwords)
26 CWDSP1670 lead vehicle technical summary from there to an off-chip d bus. part of this space is used for e ram and on-chip registers. previous cwdsp16x0 lead vehicles had two off-chip buses; c and d with programmable memory mapping by 8 kword blocks. for compatibility with the software written for those lead vehicles, two mapping modes are provided in the CWDSP1670 lead vehicle, data memory map compatibility (dmmc) and normal modes. figure 13 shows the data memory map and ta b l e 2 provides details about each memory range. figure 13 data memory map 0xffff 0xf800 0xf400C0xf7ff 0xf000C0xf3ff 0xefff 0xe000 0xdfff 0xc000 0xbfff 0xa000 0x9fff 0x8000 0x7fff 0x0000 on-chip y ram lead vehicle registers i/o space (1 kword) on-chip x ram block 4 (8 kwords) block 5 (8 kwords) on-chip e ram blocks 0C3 block 6 block 7 (8 kwords) 0xffff 0xe000 d bus (4 kwords) (32 kwords) (8 kwords) (2 kwords) 0xf000 0xec00C0xefff on-chip y ram i/o space (1 kword) 0xffff 0xe000 d bus (2 kwords) (4 kwords) lead vehicle registers 0xe800C0xebff 0xe7ff block 7 in dmmc mode block 7 in normal mode
CWDSP1670 lead vehicle technical summary 27 table 2 data memory allocation block range (dmmc mode/ normal mode) size (words) mapping wait states 0C3 0x0000C0x7fff 32 k on-chip x ram 0 4 0x8000C0x9fff 8 k d bus 1C16 (w4 + 1) 5 0xa000C0xbfff 8 k d bus 1C16 (w5 + 1) 6 0xc000C0xdfff 8 k on-chip e ram 0C16 1 (w6 + 1) 1. when the m6 bit in the r3 register is set, the number of wait states is controlled by the setting of the w6 ?eld in the r1 register. when m6 is cleared, there are no wait states. 7 0xe000C0xefff/ 0xe000C0xe7ff 4k/ 2k d bus 1C16 (w7 + 1) 0xf000C0xf3ff/ 0xe800C0xebff 1 k d bus i/o space 2C16 (wio + 1) 0xf400C0xf7df 992 on-chip reserved 0 0xf7e0C0xf7e3/ 0xec00C0xec03 4 on-chip d bus i/f registers 0 0xf7e4/ 0xec04 1 on-chip cgu register 0 0xf7e5/ 0xec05 1 on-chip reserved 0 0xf7e6/ 0xec06 1 on-chip mode id register 0 0xf7e7/ 0xec07 1 on-chip output port register 0 0xf7e8C0xf7eb/ 0xec08C0xec0b 4 on-chip timer registers 0 0xf7ecC0xf7ff/ 0xec0cC0xefff 20/ 1012 on-chip reserved 0 0xf800C0xffff/ 0xf000C0xffff 2k/ 4k on-chip y ram 0
28 CWDSP1670 lead vehicle technical summary blocks 0-3, the lower 32 kwords of data address space, are fully mapped as on-chip, closely-coupled, zero wait-state, x ram, connected through the CWDSP1670 core x bus. blocks 4 and 5 are mapped onto the CWDSP1670 cores e bus and, from there to the off-chip d bus. the w4 and w5 ?elds in the r1 register (see page 19 ) determine how many wait states (1C16) are inserted during a transaction in each block. each block is 8 kwords in length. block 6 is mapped to the on-chip e ram. when the m6 bit in the r3 register is set, the w6 ?eld in the r1 register is programmed for the number of wait states (1C16). when m6 is cleared, there are no wait states regardless of the value in the w6 ?eld. this feature allows the lead vehicle to operate at 80 mhz with a single wait state on the e memory or at <60 mhz with all of the memory (x,y,e,i and p) within the lead vehicle zero wait-stated. the lower section of block 7 is mapped onto the CWDSP1670 cores e bus and from there to the off-chip d bus, i/o space, and on-chip register addresses. the i/o space and register addresses take up 2 kwords above the d bus. the remainder is used for on-chip y ram. in dmmc mode, y ram is 2 kwords so the ?rst 4 kwords of this block can be mapped to the d bus. in normal mode, y ram is 4 kwords so only the ?rst 2 kwords of block 7 can be mapped to the d bus. the w7 ?eld in the r1 register (see page 19 ) determines how many wait states (1C16) are inserted during a transaction on the d bus. the w7 ?eld also determines how many wait states (1C16) are inserted during a transaction on the i/o space. reading from and writing to memory areas marked reserved in ta b l e 2 will have no effect on the operation of the CWDSP1670 lead vehicle. data read from these areas will be unde?ned. 6 functional description this section describes the lead vehicles functional blocks in more detail than is provided in section 2, functional overview. refer to that section for an overview and interconnection of the functional blocks
CWDSP1670 lead vehicle technical summary 29 6.1 core overview the CWDSP1670 is a 16-bit, ?xed-point digital signal processor (dsp) core designed for middle-end to high-end telecommunications and consumer applications. this core provides a low-cost, high-performance solution for applications where low-power, high integration, and portability are a necessity. this core is a component of the lsi logic coreware ? library, which contains cores for control, high-speed communication, and mixed-signal functions to complement quick time-to-market, customizable solutions. the CWDSP1670 dsp core is designed by lsi logic to be fully compatible with the dsp group oakdspcore ? instruction set architecture allowing direct porting of existing code. the oakdspcore family of cores are modi?ed harvard architectures, based on dsp groups pinedspcore ? architecture. the CWDSP1670 architecture contains dedicated buses for program and data memory. the core, shown in figure 14 , is composed of the following major components: data bus unit (dbu) address arithmetic unit (aau) program control unit (pcu) computation/bit manipulation unit (cbu) scanice unit (su) on chip emulation module (ocem) instruction bus unit (ibu) clock control unit (ccu) interrupt control unit (icu) the dbu interfaces internal core components to the off-core x, e, and y data memories and peripherals. each memory interface includes an address bus; a separate input and output data bus; memory, read, and write enables; and a synchronous/asynchronous mode select. sixteen memory bank enable outputs associated with contiguous, 4096-word, memory areas provide faster memory selection. the core has a data address space of 64 kwords. the x/y/e memory con?guration input strap pins de?ne the address boundaries between the x, e, and y data memories for the core.
30 CWDSP1670 lead vehicle technical summary the aau contains the general purpose registers, stack pointer, and index register. it also contains two identical arithmetic units to generate sequences of addresses using the aau registers. two addresses may be generated on each cycle for simultaneous access of both x- or e- memory and y-memory spaces. the pcu controls the sequencing of the core program. it fetches instructions; generates program memory addresses; handles interrupts with the icu; and sequences branches, calls, and instruction repeats. the pcu generates the controls for the rest of the CWDSP1670 dsp core. figure 14 CWDSP1670 dsp core block diagram the cbu contains arithmetic, bit, and word manipulation logic and the accumulators. it includes the multiplier alu, barrel shifter, bit function unit (bfu), and the ax and bx accumulators. there is also a saturation unit and bus alignment/sign extension logic. wait control master clock e wait out e wait computation/ address program data bus unit (dbu) xdbi xdbo xab ydbi ydbo yab edbi edbo eab exrdi exrdo core_clk instruction bus unit (ibu) idbi idbo iab pdbi pdbo pa b scanice scanice addr and data on-chip emulation x data space bus y data space bus e data space bus external register interface module (ocem) x/y/e memory con?guration arithmetic unit (aau) bit-manipulation unit (cbu) control unit (pcu) unit (su) ints and int acks clock control unit (ccu) clocks out interrupt control unit (icu) i/p memory con?guration request instruction bus interfaces
CWDSP1670 lead vehicle technical summary 31 the CWDSP1670 dsp core incorporates support for both the standard oakdspcore combo debug interface (cdi) and the lsi logic scanice in-circuit debugging systems. the scanice unit (su) uses the serial test scan chain and on-chip emulation module (ocem) to provide full debug functionality without the need for off-chip parallel buses, dual-ported memory or a monitor program. single-stepping, interrupt, repeat loop, trap, program, data and address value match breakpoint facilities are all provided. scanice is fully integrated into the CWDSP1670 core and is 100% compatible with the standard oakdspcore system development software tools. note: the CWDSP1670 lead vehicle supports only scanice debug. the ibu interfaces internal core components to the off-core i and p program memories. each memory interface includes an address bus; a separate input and output program data bus; memory, read, and write enables; 16 memory bank enables; and a synchronous/asynchronous mode select. the core has a program address space of 64 kwords. the i/p memory con?guration input strap pins de?ne the address boundary between the i and p program memories to the core. note: the CWDSP1670 lead vehicle internal memories are all synchronous. the ccu generates all the clocks for the core and the output clocks from the master clock input. it also implements the wait functionality. connecting the edb_wait_out pin to the edb_wait_req pin causes an automatic, single, wait state in each e bus access. the ccu also supplies optimized clocks for data and program memory access. clock division and clock stop modes are not provided by the core. this ensures that the core is fully static and provides ?exibility for power-optimized clock control logic to be implemented off-core. the icu handles the interrupt protocols for each of the six interrupts and generates a separate acknowledge signal for each one. the icu generates the interrupt vector and status signal for the pcu and also prioritizes incoming interrupts. note: this functionality can be seen using the edb_wait_en input of the lead vehicle.
32 CWDSP1670 lead vehicle technical summary 6.2 clock generator unit all clocks in the lead vehicle are derived from the input master clock (mclk) by the clock generation unit (cgu). clocking inside the CWDSP1670 core is isolated from the rest of the lead vehicle. the specially-generated, moving-edge, memory clocks are only used within the lead vehicle for the closely coupled memories. all transactions on the e bus interface between the core and the rest of the lead vehicle have at least one inserted wait state except for the e ram which can be programmed for 0-16 wait states. the cgu contains logic that interrupts its output clock to the core when the s0 or s1 bit in the cgu register is set and to restart the core input clock when it receives an interrupt on the int0C3 or nmi inputs as programmed into the cgu register. 6.3 d bus interface the d bus interface buffers the e bus data and address lines off chip for the selected d bus address ranges. these ranges are selected by the dmmc_mode input signal (see page 17 ) and bits in the r3 register of the interface (see page 20 ). one kword of d bus space is for i/o and the remainder is for memory. the interface also generates asynchronous read, write, and chip enable signals for both the d bus space and i/o space. figure 15 shows the interface signals. they include a 16-bit address and bidirectional data bus, memory chip select and read/write enables, i/o chip select and read/write enables, and a dma request input and bus grant output. the data or i/o controls (chip enable, read, and write) become active in the appropriate address ranges.
CWDSP1670 lead vehicle technical summary 33 figure 15 d bus interface signals the interface also controls the generation of wait states for d bus device accesses. the number of wait states generated for each block of d bus memory space is determined by a four-bit ?eld in the r1 register (see page 19 ) of the d bus interface. another 4-bit ?eld in the r2 register (see page 19 ) controls the number of wait states for i/o space accesses. the ddma_n input allows an off-chip device to gain control over the d bus. when this signal is asserted, the CWDSP1670 core is wait-stated when it writes to or reads from the d bus. the d bus data and address lines are tristated by the CWDSP1670 lead vehicle after the completion of the current instruction. the core and buses remain in this state until the next rising edge of mclk after ddma_n is released. figures 16 through 19 show the timing for the various d bus read and write transactions. da[15:0] dd[15:0] dc_n dr_n dw_n d_dma_n ioc_n ior_n iow_n d bus interface d_dma_grant CWDSP1670lv
34 CWDSP1670 lead vehicle technical summary figure 16 d bus data read timing figure 17 d bus data write timing oak_clk oak_clk eab[15:0] edbi[15:0] ere da[15:0] dd[15:0] dr_n wait_ctl (internal) (off-chip ref) oak_clk oak_clk eab[15:0] edbo[15:0] ewe da[15:0] dd[15:0] dw_n wait_ctl (internal) (off-chip ref)
CWDSP1670 lead vehicle technical summary 35 figure 18 d bus i/o read timing figure 19 d bus i/o write timing oak_clk oak_clk eab[15:0] edbi[15:0] ere da[15:] dd[15:0] ior_n wait_ctl (internal) (off-chip ref) oak_clk oak_clk eab[15:0] edbo[15:0] ewe da[15:0] dd[15:0] iow_n wait_ctl (internal) (chip pin)
36 CWDSP1670 lead vehicle technical summary 6.4 timer a timer with three memory mapped registers resides in e bus space. the timer generates an interrupt when its count reaches zero. this interrupt is routable to any of the user de?ned interrupts (int0, int1, int2, int3, or nmi) under control of the timer control register (see page 23 ). the input clock to the timer is mclk gated by the clkout_en input signal. the timer clock and timer_clk output of the chip are enabled when clkout_en is high. the timer has two, 4-bit prescalers which can be enabled or disabled using the timer control register. each prescaler divides the clock input to the timer by 16. if only one prescaler is required, then prescaler 1 should be enabled. the timer has a modulo count capability with a 16-bit, modulo, reload value speci?ed in the timer reload register (see page 23 ). another bit in the timer control register determines whether the timer operates in periodic or single count-down mode. in periodic mode, the timer counts down to zero, reloads the value speci?ed in the timer reload register, and starts counting down again. in single count-down mode, the counter stops when it reaches zero and clears the timer enable bit. the timer may also be halted at any point and restarted by clearing and resetting the enable bit in the timer control register. restart can continue from the stop count or from the reload value depending on the state of the disable reload after stop bit in the timer control register. the timer control register also contains a timer stopped indicator bit. the timer count registers are two 16-bit registers that are continually updated to the current timer count. 6.5 output port the output port includes a 16-bit register in the d bus address space and eight, general-purpose output signals, outp[7:0]. the states on the output pins directly re?ect the states of the ?rst eight bits in the register. these outputs may be used as general purpose outputs or to perform bank-switching when booting from d bus memories by providing the upper address bits for those memories.
CWDSP1670 lead vehicle technical summary 37 note: the boot code on the CWDSP1670 lead vehicle assumes the outp[1:0] pins carry the upper address bits for bank switching of memory on the d bus when a boot from the d bus occurs and the code size to be loaded is greater than 16383 words, as shown below: 6.6 external register interface the external register interface of the CWDSP1670 lead vehicle permits you to use four, 16-bit, external registers in your design. the interface is separated from the other data interfaces and not part of the lead vehicle memory map. the registers can be accessed by most of the CWDSP1670 instructions. figure 20 shows the timing of the interface signals. note: the external registers are not automatically cleared at reset. figure 20 external registers interface timing code size (words) outp1 (a15) outp0 (a14) 0C16383 0 0 16384C32767 0 1 32768C40151 1 0 49152C65535 1 1 core_clk sel_xr_rd[1:0] xrwx xrrx xrdi[15:0] xrdo[15:0]
38 CWDSP1670 lead vehicle technical summary 6.7 interrupts four maskable interrupts and one nonmaskable interrupt are available as chip inputs. the chip outputs acknowledges for each. all interrupt inputs at the chip level are active low. the CWDSP1670 lead vehicle supports both edge- and level-triggered interrupts. selection between these modes of operation is made using the level_int_mode input. any of the interrupt inputs can be programmed to occur when the timer reaches zero as described in section 4.5, timer registers. see the CWDSP1670 dsp core technical manual for further detail on interrupts. note: all interrupts pass through two resynchronization ?ip-?ops clocked by the mclk input. there is no need to provide additional resynchronization off-chip. 6.8 on-chip boot rom the states of the boot_n/mp_boot and self_test_n input signals to the lead vehicle when rst_n or mp_reset is deasserted determine the boot mode as shown in ta b l e 3 . the status of the self_test_n signal is indicated by the stb bit in the r3 register (see page 20 ). 6.8.1 self-test boot the self-test boot program includes testing of all ram memories and checksum tests of the on-chip rom as well as tests of basic table 3 boot mode selection boot_n/ mp_boot self_test_n boot mode 0 0 self-test boot. CWDSP1670 executes self-test code in rom at boot. 0 1 d bus boot. CWDSP1670 executes d bus boot loading data from device located at the base of block 4 (0x8000) in d bus data mem- ory space. 1 x normal boot. CWDSP1670 executes boot code from address 0.
CWDSP1670 lead vehicle technical summary 39 CWDSP1670 core functionality and timer operation. upon completion of the testing, or at any point where a failure is detected, the code sets up self-test status indication on the ou[1:0] outputs as shown in ta bl e 4 .it then executes a brr $-1 (branch to self) instruction, driving the chips brrm1 output high to indicate completion of the self test. 6.8.2 boot from d bus d bus booting uses an approach similar to that which was used for c bus booting on previous cwdsp16xx lead vehicles. the boot code reads: an initialization value for the r1 register from address 0x8000. the length of the program to be loaded from the d bus device at address 0x8001. the program load address from 0x8002. the run address from 0x8003. the program is then copied from the d bus device starting at address 0x8004 into program ram at the speci?ed load address. once the program has been copied, the boot code branches to the speci?ed run address. to support loading of large programs from the d bus, the boot code assumes that the outp[1:0] output pins of the CWDSP1670 lead vehicle are being used for addressing purposes if the code length is greater than 16383 words in length. see section 3.6, user i/o interface, for further information. table 4 self-test status outputs ou[1:0] status 0b00 all tests pass 0b01 data memory failure(s) 0b10 program memory or rom failure(s) 0b11 other failure(s)
40 CWDSP1670 lead vehicle technical summary 6.8.3 rom guard there is a brr -1 instruction at the start of the boot rom (address 0xfc00). this branch prevents the core from accidently running into the boot rom area. 6.9 scanice interface the scanice i/o signals of the CWDSP1670 core are brought out to the lead vehicle pins. the standard six signals, compatible with the existing pdic card, are provided. two additional scanice control and monitor signals are also made available. see section 3.8, scanice interface. 7 sample boot program figure 21 shows a ?owchart for the boot process. sample boot code is provided following the ?owchart.
CWDSP1670 lead vehicle technical summary 41 figure 21 lead vehicle boot flow rst_n deasserted set boot bm=1 boot_n=1 boot_n=0 examine stb stb=0 run from program address 0 hardware mechanisms boot rom code execution determine dmmc or normal mode set ou[1:0]=01 test data memory set ou[0:1]=10 test program memory failed? set ou[1:0]=11 test core failed? set ou[1:0]=00 failed? branch to self load dbif r1 value program length n from 0x8001, load address l from 0x8002, load run address from 0x8003 move n words starting at 0x8004 to address l note: outp[1:0] initially = 00, then is incremented by one at 16 kword boundaries. move address r -> pc (thus executing down- loaded code) stb=1 ye s ye s ye s forced brr $-3 to built-in boot routine setup stack prt. at 0xfe00 from 0x8000,
42 CWDSP1670 lead vehicle technical summary ;lsi logic;lsi logic ;26 march 1998 ;boot and softbist program ;for CWDSP1670 lead vehicle ;boot program ;r0 io base address e800/f000 ;r1 retrieval address on the d bus 8000-bfff ;r2 output port register address f7e7/ec07 ;r3 start address of y data space ;r4 target address in program space on chip 0000-fbff ;r5 beginning of program address in program space ;rb contains base address for the other memory mapped peripherals ;a0 contains program length value which is decremented with each move ;a1 used as register for doing arithmetic manipulations ;b0 contains first illegal program space address fc00 ;b1 contains the current d bus memory boundary limit address c000/bc03 ; ;************* fir definitions *************************** .equ quant 14 ; sample quantisation .equ ntaps 8 ; number of filter taps .equ nout 16 ; number of output data .equ dlysaveaddr 0x0008 .equ inaddr0x0019 .equ dlyaddr 0x0000 .equ outaddr0x0009 .equ coefaddr0xfd00 ; input samples ; apply an impulse to get the filter transfer function .code s_main .org 0x0000 br 0xfffe nop nop .org 0xfffe br main .org 0xfc00 tg1:brr -1 ;rom guard nop chksum: dw 0x9d29 parity: dw 0x913f version:dw 0x111d;version number of chip / boot rom code samples:dw fract(1.0,quant),0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 coeffs:dw fract(0.5,quant) ; h(n)=0.5 x h(n-1) dw fract(0.25,quant) dw fract(0.125,quant) dw fract(0.0625,quant) dw fract(0.03125,quant)
CWDSP1670 lead vehicle technical summary 43 dw fract(0.015625,quant) dw fract(0.0078125,quant) dw fract(0.00390625,quant) main:dint ;disable the interrupts set ##0x0300, st2 ;set output bits to indicate operation mov ##0xfe00, sp ;puts the stack pointer in y space call setmode ;calls a subroutine which sets up registers for the ;mode mode:mov (rb+#0x3), a1 ;read value of dbi r3 tstb a1l, #13 ;testing boot/self test control bit br test, eq ;goes to softbist if control is 1 rst ##0x0100, st2 ;initialize user output pins call transfer ;calls transfer routine rst ##0x0300, st2 ;initialize user output pins to indicate ;successful boot runpoint: mov r5, pc ;transfer start address to pc nop ;required for above instruction nop error: brr -1 ;something has gone wrong nop ;************************************************************************** setmode:mov ##0xf7e0, rb ;starts the check for id mode mov ##0xf000, r0 ;sets up io base address for dmmc mode mov ##0xf800, r3 ;sets y data space address mov r3, a1 ;move y address value into a1 mov ##0xf7e6, r1 ;read the contents of id register into r2 mov (r1), r2 mov a1l, (rb+#0x06) ;try to write value to the id register mov (rb+#0x06), a1 ;read back the value in the id register into a1 cmp rb, a1 ;if the values are the same then id register ;correct, should not read io base address value ret eq ;return if the test is ok mov r2, (r1) ;move the original value back to the tested address mov pc, cfgj mov ##0xec00, rb ;assuming normal mode otherwise mov ##0xe800, r0 ;sets up io base address for normal mode mov ##0xf000, r3 ;sets y data space address mov r3, a1 ;move y address value into a1 mov ##0xec06, r1 ;read the contents of id register into r2 mov (r1), r2 mov a1l, (rb+#0x06) ;try to write value to the id register mov (rb+#0x06), a1 ;read back the value in the id register into a1 cmp rb, a1 ;if the values are the same then id register ;correct, should not read io base address value ret eq ;return if the test is ok mov r2, (r1) ;move the original value back to the tested address mov pc, cfgj br error
44 CWDSP1670 lead vehicle technical summary ;************************************************************************* transfer: mov ##0x8000, r1 ;move first byte add of dbus address into r1 mov rb, a0 ;move mode base address in to a0 add #0x07, a0 ;address of the output port mov a0l, r2 ;move output port address into r2 mov (r2), a0l ;move contents of output port register to a0 rst ##0x0003, a0l ;set output port bits 0 & 1 to 0 mov a0l, (r2) ;send the new value to the output port register mov ##0xc000, b1l ;set first dbus memory boundary mov ##0xfc00, b0l ;set highest program p address for program mov (rb+#0x01), a1 ;read value of r1 dbif mov (r1)+, a0l ;move edb wait control word into r5 and ##0x0f00, a1 ;mask bits from r1 dbif and ##0xf0ff, a0 ;mask bits from control word or a1l, a0 ;combine the control word and r1 dbif mov a0l, (rb+#0x01) ;move dbus wait states to r1 dbif mov (r1)+, a0l ;move program length into a0 mov (r1)+, r4 ;move program memory destination address mov (r1)+, r5 ;move program start address cmp #0x00, a0 ;check for 0000 utility request ret eq ;go on to the run 0000 utility dec a0 ;decrement program length control word mov a0l, y ;set up counter for loop bkrep y, >%tag1-1 ;repeat the sequence for the length of prog mov r1, a1l ;checking for dbus memory boundarys cmpu b1l, a1 ;check for dbus boundary addresses call bound, ge ;go to subroutine if dbus boundary is met tag2: movd (r1)+, (r4)+ ;move data memory to program memory %tag1:ret bound:mov(r2), a1l ;read the value of the output port register mov ##0x8000, r1 ;start on the next ram bank at address 8000 tstb a1l, #0x01 ;test bit 1 br new, neq tstb a1l, #0x00 ;test bit 0, precaution br error, eq ;should not have reached here with this value mov pc, cfgj mov ##0xbc03, b1l ;change highest address for reading from dbus new:inc a1 ;point at the next ram bank mov a1l, (r2) ;write new bank bits to output port register ret ;go back to the loading routine ;************************************************************************** ;soft bist program test:rst ##0x0200, st2 ;reset value of user output pins mov ##0xfe00, sp mov ##0x0000, a0l ;x first 4k parameter indicates start address mov ##0x1000, a1l ;parameter indicates length of block i call test_dmem_rr4k16 mov ##0x1000, a0l call test_dmem_rr4k16 mov ##0x2000, a0l call test_dmem_rr4k16 mov ##0x3000, a0l call test_dmem_rr4k16
CWDSP1670 lead vehicle technical summary 45 mov ##0x4000, a0l call test_dmem_rr4k16 mov ##0x5000, a0l call test_dmem_rr4k16 mov ##0x6000, a0l call test_dmem_rr4k16 mov ##0x7000, a0l ;x 8th 4k start address block viii call test_dmem_rr4k16 mov pc, cfgj mov ##0xc000, a0l ;e 1st 4k start address block i call test_dmem_rr4k16 mov ##0xd000, a0l ;e 2nd 4k start address block ii call test_dmem_rr4k16 mov ##0x4000, sp ;y 4k/2k move stack pointer to x mov r3, a0l ;r3 contains base address of y memory cmpv ##0xf800, r3 ;check to determine size of y memory moda shr, a1, eq ;halves value if y=2k call test_dmem_rr4k16 rst ##0x0100, st2 ;reset value of user output pins set ##0x0200, st2 ;indicate program memory testing mov ##0x0000, a0l ;start of i program memory mov ##0x4000, a1l ;length of block i call test_pmem_rr16k16 mov ##0x4000, a0l ;start of i program memory block ii call test_pmem_rr16k16 mov ##0x8000, a0l ;start of p program memory block i call test_pmem_rr16k16 mov ##0xc000, a0l ;start of p program memory block ii mov ##0x3c00, a1l ;length of block ii call test_pmem_rr16k16 mov pc, cfgj call crom set ##0x0100, st2 ;indicate other tests in progress call fir call crit ; insert lv register tests rst ##0x0300, st2 stop:brr -1 ;halt the boot routine nop
46 CWDSP1670 lead vehicle technical summary ;************************************************************************* ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; rcs $id: bb_rout.asm,v 1.13 1998/09/30 14:23:57 kerryl exp $ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; filename: rr4k16d_test.asm ; ; purpose: memory dependend algorithms library ; ; context: march c asic-driven memorytest ; ; author: lsisoftbist rambist software code compiler ; ; copyright (c), lsi logic, 1996 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; update history ; ; rcs $log: bb_rout.asm,v $ ; rcs revision 1.13 1998/09/30 14:23:57 kerryl ; rcs adding functionality to boot sequence ; rcs ; rcs revision 1.12 1998/07/30 15:16:08 kerryl ; rcs update to softbist for new memories ; rcs ; rcs revision 1.11 1998/07/20 10:33:12 kerryl ; rcs change to boot up routine to satisfy gls ; rcs ; rcs revision 1.10 1998/06/23 16:32:51 kerryl ; rcs br change ; rcs ; rcs revision 1.9 1998/06/11 08:55:41 kerryl ; rcs modifying the boot version value and checksums ; rcs ; rcs revision 1.8 1998/06/03 16:05:27 kerryl ; rcs modifying the boot version value and checksums ; rcs ; rcs revision 1.5 1998/05/12 16:41:51 kerryl ; rcs change in script ; rcs ; rcs revision 1.4 1997/09/26 14:59:09 wiesner ; rcs added checkboard background option ; rcs ; rcs revision 1.3 1997/09/19 12:53:32 wiesner ; rcs alpha version for marco ; rcs ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; march c testroutine ; prototype: void test_dmem_rr4k16(void *sa, unsigned int sz, error_code* err) ; ; formal parameters --------------------------------------------------------
CWDSP1670 lead vehicle technical summary 47 ; ; return <== a0l (void dummy) ; &sa ==> a0l ; sz ==> a1l ; &err ==> b0l ; ; local used registers ----------------------------------------------------- ; ; r0 = pointer tp testpattern ; r1 = latch addresspointer ; r2 = row size in words ; r3 = temp location ; r4 = pointer to address ; y = size register ; r5 = free pointer ; sv = shift value test_dmem_rr4k16: push r0 push r1 push r2 push r3 push r4 push r5 push rb push y push sv push b0l push a0l push a1l ; initialize addresspointer mov a0l, r4 ; calculate shifter value and/or (pass)loopcounter moda shr4, a1 ;moda shr, a1 moda dec,a1 mov a1l,y mov ##0x03, r2 ; store addresspointer mov r4, r1 ; pass 1: increasing addresses -------------------------------------------------- mov ##0xffff, a1l mov ##0x0000, a0l bkrep y,>%lab-1 bkrep r2, >%lab3-1 mov a1l, (r4) ; write pattern cmpu (r4)+, a1
48 CWDSP1670 lead vehicle technical summary br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)+, a0 br stopd, neq nop %lab3: bkrep r2, >%lab2-1 mov a0l, (r4) ; write pattern cmpu (r4)+, a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)+, a1 br stopd, neq nop %lab2: nop %lab:mov r1, r4 ; restore addresspointer ; pass 2: increasing addresses -------------------------------------------------- bkrep y,>%lab-1 bkrep r2, >%lab3-1 cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)+, a0 br stopd, neq cmpu (r4), a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)+, a1 br stopd, neq nop %lab3: bkrep r2, >%lab2-1 cmpu (r4), a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)+, a1 br stopd, neq cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)+, a0 br stopd, neq nop %lab2: nop %lab: mov r1, r4 ; pass 3: increasing addresses -------------------------------------------------- bkrep y,>%lab-1 bkrep r2, >%lab3-1 cmpu (r4), a0
CWDSP1670 lead vehicle technical summary 49 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)+, a1 br stopd, neq cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)+, a0 br stopd, neq nop %lab3: bkrep r2, >%lab2-1 cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)+, a0 br stopd, neq cmpu (r4), a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)+, a1 br stopd, neq nop %lab2: nop %lab: modr (r4)- ; pass 4: decreasing addresses -------------------------------------------------- mov r4, r1 bkrep y,>%lab-1 bkrep r2, >%lab3-1 cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)-, a0 br stopd, neq cmpu (r4), a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)-, a1 br stopd, neq nop %lab3: bkrep r2, >%lab2-1 cmpu (r4), a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)-, a1 br stopd, neq cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)-, a0 br stopd, neq nop
50 CWDSP1670 lead vehicle technical summary %lab2: nop %lab: mov r1, r4 ; pass 5: decreasing addresses -------------------------------------------------- bkrep y,>%lab-1 bkrep r2, >%lab3-1 cmpu (r4), a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)-, a1 br stopd, neq cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)-, a0 br stopd, neq nop %lab3: bkrep r2, >%lab2-1 cmpu (r4), a1 br stopd, neq mov a0l, (r4) ; write pattern cmpu (r4)-, a0 br stopd, neq cmpu (r4), a0 br stopd, neq mov a1l, (r4) ; write pattern cmpu (r4)-, a1 br stopd, neq nop %lab2: nop %lab: test_dmem_rr4k16_end: pop a1l pop a0l pop b0l pop sv pop y pop rb pop r5 pop r4 pop r3 pop r2 pop r1 pop r0 ret stopd: brr -1 nop
CWDSP1670 lead vehicle technical summary 51 ;*************************************************************** ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; rcs $id: bb_rout.asm,v 1.13 1998/09/30 14:23:57 kerryl exp $ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; filename: rr16k16p_test.asm ; ; purpose: memory dependend algorithms library ; ; context: march c asic-driven memorytest ; ; author: lsisoftbist rambist software code compiler ; ; copyright (c), lsi logic, 1996 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; update history ; ; rcs $log: bb_rout.asm,v $ ; rcs revision 1.13 1998/09/30 14:23:57 kerryl ; rcs adding functionality to boot sequence ; rcs ; rcs revision 1.12 1998/07/30 15:16:08 kerryl ; rcs update to softbist for new memories ; rcs ; rcs revision 1.11 1998/07/20 10:33:12 kerryl ; rcs change to boot up routine to satisfy gls ; rcs ; rcs revision 1.10 1998/06/23 16:32:51 kerryl ; rcs br change ; rcs ; rcs revision 1.9 1998/06/11 08:55:41 kerryl ; rcs modifying the boot version value and checksums ; rcs ; rcs revision 1.8 1998/06/03 16:05:27 kerryl ; rcs modifying the boot version value and checksums ; rcs ; rcs revision 1.5 1998/05/12 16:41:51 kerryl ; rcs change in script ; rcs ; rcs revision 1.4 1997/09/26 14:59:09 wiesner ; rcs added checkboard background option ; rcs ; rcs revision 1.3 1997/09/19 12:53:32 wiesner ; rcs alpha version for marco ; rcs ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; march c testroutine ; prototype: void test_pmem_rr16k16(void *sa, unsigned int sz, error_code* err) ; ; formal parameters -------------------------------------------------------- ;
52 CWDSP1670 lead vehicle technical summary ; return <== a0l (void dummy) ; &sa ==> a0l ; sz ==> a1l ; &err ==> b0l ; ; local used registers ----------------------------------------------------- ; ; r0 = pointer tp testpattern ; r1 = latch addresspointer ; r2 = adr to errorstruct ; r3 = temp location ; r4 = pointer to address ; y = size register ; r5 = free pointer ; sv = shift value test_pmem_rr16k16: push r0 push r1 push r2 push r3 push r4 push r5 push rb push y push sv push b0l push a0l push a1l ; initialize addresspointer mov a0l, r4 ; calculate shifter value and/or (pass)loopcounter moda shr4, a1 moda shr, a1 ;moda shr, a1 moda dec,a1 mov a1l,y mov ##0x07, r2 mov ##0x0000, r3 ; store addresspointer mov r4, r5 ; pass 1: increasing addresses -------------------------------------------------- mov ##0x0001,r0 mov ##0x0002, r1 mov ##0xff00, a1l mov a1l,(r0) mov ##0x00ff, a0l mov a0l, (r1) bkrep y,>%lab-1
CWDSP1670 lead vehicle technical summary 53 bkrep r2, >%lab3-1 movd (r0), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a1 br stopp, neq movd (r1), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a0 br stopp, neq nop %lab3: bkrep r2, >%lab2-1 movd (r1), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a1 br stopp, neq nop %lab2: nop %lab:mov r5, r4 ; restore addresspointer ; pass 2: increasing addresses -------------------------------------------------- bkrep y,>%lab-1 bkrep r2, >%lab3-1 movp (r4), (r3) cmpu (r3), a1 br stopp, neq movd (r1), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a0 br stopp, neq movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)+,(r3) cmpu (r3), a1 br stopp, neq nop %lab3: bkrep r2, >%lab2-1 movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a1 br stopp, neq movp (r4), (r3) cmpu (r3), a1 br stopp, neq movd (r1), (r4) ; write pattern
54 CWDSP1670 lead vehicle technical summary movp (r4)+, (r3) cmpu (r3), a0 br stopp, neq nop %lab2: nop %lab: mov r5, r4 ; pass 3: increasing addresses -------------------------------------------------- bkrep y,>%lab-1 bkrep r2, >%lab3-1 movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a1 br stopp, neq movp (r4), (r3) cmpu (r3), a1 br stopp, neq movd (r1), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a0 br stopp, neq nop %lab3: bkrep r2, >%lab2-1 movp (r4), (r3) cmpu (r3), a1 br stopp, neq movd (r1), (r4) ; write pattern movp (r4)+, (r3) cmpu (r3), a0 br stopp, neq movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)+,(r3) cmpu (r3), a1 br stopp, neq nop %lab2: nop %lab: modr (r4)- ; pass 4: decreasing addresses -------------------------------------------------- mov r4, r5 bkrep y,>%lab-1 bkrep r2, >%lab3-1 movp (r4), (r3) cmpu (r3), a1 br stopp, neq
CWDSP1670 lead vehicle technical summary 55 movd (r1), (r4) ; write pattern movp (r4)-, (r3) cmpu (r3), a0 br stopp, neq movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)-,(r3) cmpu (r3), a1 br stopp, neq nop %lab3: bkrep r2, >%lab2-1 movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)-, (r3) cmpu (r3), a1 br stopp, neq movp (r4), (r3) cmpu (r3), a1 br stopp, neq movd (r1), (r4) ; write pattern movp (r4)-, (r3) cmpu (r3), a0 br stopp, neq nop %lab2: nop %lab: mov r5, r4 ; pass 5: decreasing addresses -------------------------------------------------- bkrep y,>%lab-1 bkrep r2, >%lab3-1 movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)-, (r3) cmpu (r3), a1 br stopp, neq movp (r4), (r3) cmpu (r3), a1 br stopp, neq movd (r1), (r4) ; write pattern movp (r4)-, (r3) cmpu (r3), a0 br stopp, neq nop %lab3: bkrep r2, >%lab2-1 movp (r4), (r3) cmpu (r3), a1
56 CWDSP1670 lead vehicle technical summary br stopp, neq movd (r1), (r4) ; write pattern movp (r4)-, (r3) cmpu (r3), a0 br stopp, neq movp (r4), (r3) cmpu (r3), a0 br stopp, neq movd (r0), (r4) ; write pattern movp (r4)-,(r3) cmpu (r3), a1 br stopp, neq nop %lab2: nop %lab: test_pmem_rr16k16_end: pop a1l pop a0l pop b0l pop sv pop y pop rb pop r5 pop r4 pop r3 pop r2 pop r1 pop r0 ret stopp: brr -1 nop ;******************************************************************** ;*************************** fir *********************************** ;******************************************************************* ; inreg is register r1 ; outreg is register r2 ; dlyptr is register r0 ;------------------------------------- fir: mov ##0x0800,st1 ; init sp, page ; shift p register bits (sp) - 1 left ; (suitable to the presentation where the ; binary point is placed after the 1st bit). ; also initial page into page 0 ; dly[i] = 0 ; copy test sample data into x data memory mov ##samples, r4 mov ##inaddr,r2 rep #nout-1
CWDSP1670 lead vehicle technical summary 57 movp (r4)+,(r2)+ ; copy co-efficients into y data memory mov ##coeffs, r4 mov ##coefaddr,r3 rep #ntaps-1 movp (r4)+,(r3)+ ; clear samples buffer mov ##dlyaddr,r0 clr a0 rep #ntaps-1 mov a0l,(r0)+ ;******************** program code ************************** ; initializations for test_fir_real routine init_test_fir_real: mov ##inaddr,r3 ; r3 points to inaddr mov ##outaddr,r5 ; r5 points to outaddr ; ----------------------------------------- benchmarkinit: mov ##dlyaddr+ntaps-1,r0 ; r0 points to dly (end of buffer) mov r0,dlysaveaddr ; store dly pointer mov ##coefaddr,r4 ; r4 points to coef mov #0x11,a0l ; set modulo operations - or st2,a0 ; m0 m4 bit at st2 mov a0l,st2 ; for r0, r4 mov ##(ntaps-1)*128,cfgi ; define modi , no step mov ##(ntaps-1)*128,cfgj ; define modj , no step ; ----------------------------------------- test_fir_real: ; run fir_real benchmark nout times : bkrep #nout-1, >%testend mov (r3)+,r1 ; inreg = in[n] mov dlysaveaddr,r0 ; restore dly pointer
58 CWDSP1670 lead vehicle technical summary ;*********** fir_real sample by sample processing *************** fir_real: modr (r0)+ ;r0 points to the oldest sample mov r1,(r0) ; input new sample ; ntaps moda clrr,a0 ; a0 = 0x8000 mpy (r4)+,(r0)- ; p = h(0) * x(i) rep #ntaps-2 mac (r4)+,(r0)-,a0 ; a0 = a0 + p ; p = h(k) * x(i-k) add p,a0 ; ntaps-1 mov a0h, r2 ; outreg=y(i)= sum( h(k) x(i-k) ) k=0 benchmarkterminate: mov r0,dlysaveaddr ; store dly pointer %testend: mov r2,(r5)+ ; outreg = out[n] ; ; check results were as expected ; ; set up pointer to copy of filter co-efficients in y memory mov ##outaddr,r0 ; set up pointer to actual results in x memory mov ##coefaddr,r3 ; disable modulo addressing used by fir filter rst ##0x003f,st2 ; loop to check samples = 1/2 original co-efficients bkrep #ntaps-1, %chkloop mov (r3)+,a0 ; copy next co-efficient value into a0 shr a0 ; divide by two using a shift cmp (r0)+,a0 ; compare to output data br error,neq ; branch to error if comparison failed mov pc, cfgj nop %chkloop:nop endit:ret ;****************************************************************** ;*********************** rom check ******************************** ;****************************************************************** crom: moda clr, a0 ;clears accumulators performing the checksum modb clr, b0 mov ##0x03fb, r1 ;length of boot rom - top 4 bytes mov ##0xffff, a1 ;top of boot rom space bkrep r1,>%lab4 ;repeat for each location in rom - top 4 movp (a1l), r0 ;mov the value in rom to r0 xor r0, a0 ;perform parity operation swap(a0, b0) addl r0, a0 ;perform checksum operation
CWDSP1670 lead vehicle technical summary 59 swap(a0, b0) %lab4:dec a1 ;next memory location movp (a1l), r0 ;mov parity value into r0 cmpu r0, a0 ;compare with generated value br error ,neq ;if they are not equal quit mov b0l, a0l ;swap accumulators dec a1 ;decrement memory location movp (a1l),r0 ;mov checksum value to r0 cmpu r0, a0 ;compare with generated value br error, neq ;if they are not equal quit mov pc, cfgj ret ;successful. rom is ok ;****************************************************************** ;************************ critical path *************************** ;****************************************************************** crit: rst ##0xffff, st1 mov ##0xffff, a0 mov ##0x0001, a1 add a1l, a0 ;long carry chain in add/sub cmpv ##0x0000, a0l ;success check br error, neq sub a1l, a0 ;long carry chain in add/sub different values cmpv ##0xffff, a0l ;success check br error, neq mov pc, cfgj lpg #0x00 mov ##0xffff, r0 mov ##0x0000, r1 mov ##0x0001, r2 mov r0, (r1)+ mov r2, (r1)- mov r1, (r0)- mov r0, r4 mov r2, (r0)+ mac (r4), (r1), a1 ;a long path through the mac (r4), (r1), a1 ;multiplier mac (r1), ##0xffff, a0 ;a long path through the mac (r1), ##0xffff, a0 ;multiplier cmpv ##0xffff, a0l br error, neq cmpv ##0x0000, a1l br error, neq addv ##0x0001, (r1) ;long carry chain in add/sub using memory subv ##0xffff, (r0) ;paths mov (r1)+, a0l mov (r0)-, r3 sub r3, a0 cmpv ##0xffff, a0l ;success check br error, neq mov pc, cfgj mov ##0x5555, r4 mov ##0x0000, sp
60 CWDSP1670 lead vehicle technical summary mov ##0xffff, rb push r4 ;pushing and popping on ffff/0000 memory pop a0l ;boundary. completely invert address bits cmp r4, a0 ;in consecutive instructions br error, neq mov pc, cfgj mov a0l, (rb+#0x01) ;reading and writing memory locations mov (rb+#0x01), a0 ;around the ffff/0000 memory boundary cmp r4, a0 ;using the indexed addressing logic br error, neq mov pc, cfgj mov ##0xfff4, sv ;sets up for right shift movs 0x00, b0 ;takes value from mem through barrel shifter ;into accumulator divs 0x01, a0 ;another long path rep #3 ;repeat next instruction 4 times maxd a1, (r0)+, gt ;compare across ffff/0000 boundary add a0l, a1 set ##0x0080, st2 shr a1 add b0l, a1 mov a1l, (r0) mov mixp, a0 chng ##0xffff, (r0) cmp (r0), a0 br error, neq mov pc, cfgj moda clr, a0 moda clr, a1 mov ##0xffff, r4 mov ##0x0000, r0 mov ##0x1111, r2 mov ##0x0005, r1 mov ##0x0002, r3 mov ##0x5555, r5 mov r1, (r0)+ mov r3, (r0)- mov r2, (r4)- mov r5, (r4)+ mac (r4)-, (r0)+, a0 mac (r4)+, (r0)-, a1 mac (r4), (r0)+, a0 mac (r4), (r0)+, a1 sub a1l, a0 msu (r4), (r0), a1 mac (r4), (r0), a0 cmpv ##0xeef0, a0l br error, neq cmpv ##0x8888, a1l br error, neq mov ##0x3fff, sp ret
CWDSP1670 lead vehicle technical summary 61 ;****************************************************************** ;***************** utilities ************************************** ;****************************************************************** risr: reti ;redundant interrupt service routine ;****************************************************************** cisrr:addv ##0x0001, (r0) ; redundant interrupt service routine reti ; which increments a indirect memory location ;****************************************************************** cisrm:push a0l ; redundant interrupt service routine push a0h ; which increments the contents of a mov [##0xffff], a0 ;specific memory location moda inc, a0 mov a0l, [##0xffff] pop a0h pop a0l reti ;****************************************************************** dnfl:mov ##0xffff, lc ;do nothing fast loop rep lc nop brr -3 ret ;****************************************************************** scrs0:push a0l ;stop clock routine using s0 push a0h push rb push r0 push r2 push r3 call setmode mov (rb+#0x04), a0 set ##0x0080, a0l mov a0l, (rb+#0x04) nop nop pop r3 pop r2 pop r0 pop rb pop a0h pop a0l ret ;****************************************************************** scrs1:push a0l ;stop clock routine using s1 push a0h push rb push r0 push r2 push r3 call setmode
62 CWDSP1670 lead vehicle technical summary mov (rb+#0x04), a0 set ##0x0100, a0l mov a0l, (rb+#0x04) nop nop pop r3 pop r2 pop r0 pop rb pop a0h pop a0l ret ;****************************************************************** rver:push r5 ;return version number of chip/rom code push a0l push a0h mov ##0xfc04, a0 movp (a0l), r5 pop a0h pop a0l ret ;****************************************************************** ebws:push r5 push r1 push r2 push r4 call setmode mov ##0x0000, r5 mov ##0xffff, a0 mov ##0x0001, r1 mov rb, a1 add ##0x0009, a1 mov a1l, r4 mov r5, (r4)- mov a0l, (r4)+ mov r1, (r4)+ mov (r4), b0 sub b0l, a0 pop r4 pop r2 pop r1 pop r5 ret ;******************************************************************
CWDSP1670 lead vehicle technical summary 63 8 speci?cations this section presents the electrical and mechanical speci?cations for the CWDSP1670 lead vehicle. 8.1 electrical characteristics tables 5 through 8 describe the electrical speci?cations for the lead vehicle. table 5 absolute maximum ratings symbol parameter limits units v dd4 dc supply voltage for i/o buffers -0.3 to +3.9 v v dd2 dc supply voltage for core and chip logic -0.3 to +2.75 v v in input voltage -1.0 to v dd4 +0.3 v i in dc input current -10 to +10 ma t stgp storage temperature, plastic -40 to +125 c table 6 recommended operating conditions for 60 mhz maximum operating frequency symbol parameter limits units v dd4 dc supply voltage +3.00 to 3.60 v v dd2 dc supply voltage +2.25 to +2.75 v t a ambient temperature, commercial -20 to +85 c
64 CWDSP1670 lead vehicle technical summary table 7 recommended operating conditions for 80 mhz maximum operating frequency 1 symbol parameter limits units v dd4 dc supply voltage +3.15 to 3.45 v v dd2 dc supply voltage +2.50 to +2.75 v t a ambient temperature, commercial -20 to +40 c 1. edb_wait_en must be set to logic 1 table 8 capacitance symbol parameter 1 min max units c in input capacitance C5pf c out output capacitance C10pf c io i/o bus capacitance C15pf 1. measurement conditions are v in =v,t a = 25 ?c, and clock frequency = 80 mhz. table 9 dc characteristics symbol parameter condition 1 min typ max units v ih high level input voltage C 2.0 C C v clkin high input level C 2.0 C C v il low level input voltage C C C 0.8 v clkin low input level C C C 0.8 v oh high level output voltage i oh = -4.0 ma 2.4 4.5 C v v ol low level output voltage i ol = 4.0 ma C 0.2 0.4 v
CWDSP1670 lead vehicle technical summary 65 8.2 ac timing all of the timing in this section is referenced to the internal oak_clk/clk_ug. figure 22 shows how these clocks are related. figure 22 internal clocks i il input leakage current (output and i/o pins in hi-z or input state). see note 2 -10 -1 to +1 10 ua i cc supply current, dynamic v dd4 = max f = 50 mhz C 150 C ma 1. measurement conditions are ta = 25 c, vcc = 3.3 v, gnd = 0 v, 100 pf load on clkout . 2. v dd4 = max, v in =v dd4 or v ss ,v out =v dd4 or v ss table 9 dc characteristics (cont.) symbol parameter condition 1 min typ max units symbol description typ (ns) t d_oc_int delay of internal oak_clk (wcmil) 5.3 t d_oc_ext delay of external oak_clk (wcmil) 3.0 master oak_clk oak_clk (internal) (external) master oak_clk core cgu (external) t d_oc_int t d_oc_ext
66 CWDSP1670 lead vehicle technical summary figure 23 , figure 24 , and ta b l e 1 0 specify the read and write timing of d bus accesses. figure 25 , figure 26 , and ta b l e 1 1 specify the read and write timing of d bus i/o space accesses. the timing was measured at 125?c (junction temperature) using the wcmil process and 15 pf loading on all outputs and is valid from wcmil to bcmil. figure 23 d bus read timing (1 wait state) da[15:0] dc_n dr_n t dav t dai t ddcv t ddci clk_ug oak_clk dd[15:0] t ddri t ddrv t ddds t dddh
CWDSP1670 lead vehicle technical summary 67 figure 24 d bus write timing (1 wait state) da[15:0] dd[15:0] dc_n dw_n clk_ug oak_clk t ddds t dddh t ddws t ddwi table 10 d bus read/write timing item description minimum (ns) maximum (ns) t dav d bus address valid - 8 t dai d bus address invalid: clock falling edge to address invalid 1 C t ddrv d bus read strobe valid C 7 t ddri d bus read strobe invalid 1 C t ddcv d bus chip select valid C 8 t ddcv d bus chip select invalid: clock falling edge to chip select invalid 1C t ddws d bus write strobe valid C 7 t ddwi d bus write strobe invalid 1 C t dddv d bus write data valid C 9 t dddi d bus write data invalid 1 C
68 CWDSP1670 lead vehicle technical summary figure 25 i/o space read timing (2 wait states) t ddds d bus read data setup: read data valid to read strobe rising edge 6C t dddh d bus read data hold: read strobe rising edge to read data invalid 0C table 10 d bus read/write timing (cont.) item description minimum (ns) maximum (ns) da[15:0] ioc_n ior_n clk_ug oak_clk dd[15:0] t iocv t ioci t iori t iorv t iodh t iods
CWDSP1670 lead vehicle technical summary 69 figure 26 i/o space write timing (2 wait states) table 11 i/o space read/write timing item description minimum (ns) maximum (ns) t iocv io chip select valid C 8 t ioci io chip select hold: clock falling edge to chip select invalid 1 C t iorv io read strobe valid C 7 t iori io read strobe hold: clock falling edge to write strobe invalid 1 C t iowv io write strobe valid C 7 t iowi io write strobe hold: clock falling edge to write strobe invalid 1 C t iods io read data setup: read data valid to read strobe falling edge 6 C t iodh io read data hold: read strobe falling edge to read data invalid 0 C da[15:0] dd[15:0] ioc_n iow_n clk_ug oak_clk t iowv t iowv
70 CWDSP1670 lead vehicle technical summary 8.3 package pinout and mechanical drawing ta b l e 1 2 lists the lead vehicles i/o signals in alphabetical order, shows their pin numbers and direction, and provides a brief description. ta b l e 1 3 includes the same information but is sorted by solder ball designation. figure 27 is the mechanical drawing for the lead vehicle. figure 28 shows the pin names looking into the solder balls. table 12 alphabetical signal listing signal name bond pad solder ball i/o description abort_n 55 p3 in abort input abort_out 81 p9 out abort acknowledge boot_n 54 r2 in boot control (boot from rom when low) brrm1 86 n10 out high = brr $-1 executed clk_ug 59 p4 out copy of CWDSP1670 core clock without wait states clkout_en 196 d4 in high = enable oak_clk, clk_ug, and timer_clk outputs d_dma_grant 49 p1 out high = dma has been granted d bus. da, dd, dw_n, dr_n, dc_n, iow_n, ior_n, and ioc_n are tristated. d_dma_n 47 m3 in low = external dma controller becomes d bus master da0 1 b2 out/z d bus address lines da1 2 c3 out/z da10 14 e1 out/z da11 13 f5 out/z da12 15 f4 out/z da13 16 f3 out/z da14 17 f2 out/z da15 18 f1 out/z
CWDSP1670 lead vehicle technical summary 71 da2 3 b1 out/z d bus address lines (cont.) da3 4 c2 out/z da4 6 c1 out/z da5 5 d3 out/z da6 7 d2 out/z da7 11 e5 out/z da8 8 e4 out/z da9 12 e2 out/z dc_n 44 l4 out/z d bus chip select dd0 21 g5 inout/z d bus data lines dd1 23 g2 inout/z dd10 32 j2 inout/z dd11 37 k4 inout/z dd12 35 k3 inout/z dd13 36 k2 inout/z dd14 34 k1 inout/z dd15 38 l1 inout/z dd2 22 g1 inout/z dd3 24 h5 inout/z dd4 25 h4 inout/z dd5 27 h3 inout/z dd6 28 h2 inout/z dd7 26 h1 inout/z dd8 33 j5 inout/z dd9 31 j3 inout/z table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
72 CWDSP1670 lead vehicle technical summary dmmc_mode 185 b6 in high = dmmc mode, low = normal mode dr_n 42 m1 out/z d bus read enable dw_n 41 l2 out/z d bus write enable edb_wait_en 153 b13 in high = enable the automatic, single wait state generation for e bus accesses. emem_wait 60 l6 in high = 1 wait state for e memory (m6 cleared), low = zero wait states for e memory escan_en 156 c12 in reserved escan_in 155 d12 in reserved escan_out 199 a2 out reserved ext_scan_alert 171 b9 out scanice alert ext_scan_clk 165 a11 in scanice clock ext_scan_ctl 164 b11 in scanice load control ext_scan_in 163 d10 in scanice data in ext_scan_out 169 e9 out scanice data out ext_scan_rst 166 c10 in scanice reset iack_int0_n 125 h13 out int0 acknowledge iack_int1_n 126 h15 out int1 acknowledge iack_int2_n 127 h12 out int2 acknowledge iack_int3_n 128 h11 out int3 acknowledge iack_nmi_n 129 g14 out nmi acknowledge iiddtn 195 a3 C production test im3 189 e6 in int3 mask control int0_n 191 c5 in maskable interrupt #0 int1_n 192 a4 in maskable interrupt #1 int2_n 193 d5 in maskable interrupt t#2 table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
CWDSP1670 lead vehicle technical summary 73 int3_cntx_en 190 b5 in high = int3 automatic context switch enable int3_n 194 b4 in maskable interrupt #3 int3_vec0 132 g13 in int3 vector address input int3_vec1 133 g12 in int3_vec10 144 e12 in int3_vec11 145 d14 in int3_vec12 146 c15 in int3_vec13 147 d13 in int3_vec14 148 c14 in int3_vec15 149 b15 in int3_vec2 134 f15 in int3_vec3 135 f14 in int3_vec4 136 f13 in int3_vec5 137 f12 in int3_vec6 138 e15 in int3_vec7 139 f11 in int3_vec8 142 d15 in int3_vec9 143 e13 in ioc_n 43 l3 out/z i/o chip select ior_n 45 n1 out/z i/o read enable iow_n 46 m2 out/z i/o write enable iu0 57 m5 in user input pins iu1 58 r3 in level_int_mode 158 d11 in high = level-triggered interrupt mode, low = edge-triggered interrupt mode table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
74 CWDSP1670 lead vehicle technical summary mclk 184 a6 in master input clock mp_abort 53 p2 in master processor abort control mp_boot 152 c13 in master processor boot control mp_reset 154 a14 in master processor reset control nmi_n 157 a13 in nonmaskable interrupt not connection 84 r10 C C not connected 155 d12 C C not connected 51 100 151 156 199 200 r1 n13 a15 c12 a2 a1 CC oak_clk 85 p10 out copy of CWDSP1670 core clock ocem_susp 186 c6 in high = turn off all clocks to ocem ou0 88 p11 out user output pins ou1 87 r11 out outp0 174 c8 out output port outp1 175 b8 out outp2 176 a8 out outp3 177 d8 out outp4 178 e8 out outp5 179 e7 out outp6 180 a7 out outp7 181 b7 out pprotect_en 161 a12 in high enables p bus memory protection. procout 198 b3 C process monitor pin table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
CWDSP1670 lead vehicle technical summary 75 ptst 99 p14 in production test enable ptst_te 98 r14 in production test scan chain load enable rst_n 162 c11 in reset input rst_out_n 83 l9 out synchronized to oak_clk version of rst_n scan_debug_en 172 a9 in high = enable scanice debug mode scanice_mode 170 c9 out high = scanice mode is active sel_xr_rd0 123 j12 out multiplexer control signals for read of external registers sel_xr_rd1 124 h14 out self_test_n 56 n4 in self-test boot enable stop_mode 82 n9 out indicates CWDSP1670 core is in stop mode timer_clk 84 r10 out timer input clock, gated copy of mclk tn 52 n3 C production test vdd2 C oak core 167 187 b10 d6 in +2.5 v core power vdd2 C ram/lv logic Cf6 f7 f9 f10 g6 g10 j6 j10 k6 k7 k9 k10 in +2.5 v ram/lv logic power table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
76 CWDSP1670 lead vehicle technical summary vdd4 9 19 29 39 69 79 89 97 111 121 130 140 159 182 e3 g4 j4 k5 r6 m9 m10 p13 l14 j13 g15 e14 b12 c7 in +3.3 v i/o buffer power vss 10 20 30 40 50 70 80 90 112 122 131 141 150 160 168 173 183 188 197 d1 g3 j1 l5 n2 l7 r9 n11 l11 j15 g11 e11 b14 e10 a10 d9 d7 a5 c4 f8 g7 g8 g9 h6 h7 h8 h9 h10 j7 j8 j9 k8 C ground table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
CWDSP1670 lead vehicle technical summary 77 wait_ctl_n 48 m4 in external wait control xrdi0 61 r4 in external register data in xrdi1 62 m6 in xrdi10 73 r7 in xrdi11 74 l8 in xrdi12 75 m8 in xrdi13 76 r8 in xrdi14 78 n8 in external register data in xrdi15 77 p8 in xrdi2 63 n5 in xrdi3 64 p5 in xrdi4 65 r5 in xrdi5 66 n6 in xrdi6 67 m7 in xrdi7 68 p6 in xrdi8 71 n7 in xrdi9 72 p7 in xrdo0 91 r12 out xrdo1 92 l10 out xrdo10 105 m13 out xrdo11 106 m14 out xrdo12 107 n15 out xrdo13 108 l12 out xrdo14 109 l13 out xrdo15 110 m15 out table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
78 CWDSP1670 lead vehicle technical summary xrdo2 93 p12 out external register data out (cont.) xrdo3 94 m11 out xrdo4 95 r13 out xrdo5 96 n12 out xrdo6 101 r15 out xrdo7 102 n14 out xrdo8 103 p15 out xrdo9 104 m12 out external register data out xrr0_n 113 k11 out read enable for ext. reg. #0 xrr1_n 114 l15 out read enable for ext. reg. #1 xrr2_n 115 k12 out read enable for ext. reg. #2 xrr3_n 116 k14 out read enable for ext. reg. #3 xrw0_n 117 k13 out write enable for ext. reg. #0 xrw1_n 118 k15 out write enable for ext. reg. #1 xrw2_n 119 j11 out write enable for ext. reg. #2 xrw3_n 120 j14 out write enable for ext. reg. #3 table 12 alphabetical signal listing (cont.) signal name bond pad solder ball i/o description
CWDSP1670 lead vehicle technical summary 79 table 13 signal listing by ball number solder ball bond pad signal name i/o description a1 200 not connected C C a2 199 escan_out out reserved, leave unconnected a3 195 iiddtn C production test a4 192 int1_n in maskable interrupt #1 a5 188 vss C ground a6 184 mclk in master input clock a7 180 outp6 out user output 6 a8 176 outp2 out user output 2 a9 172 scan_debug_en in enable scanice debug mode a10 168 vss C ground a11 165 ext_scan_clk in scanice clock a12 161 pprotect_en in high enables p bus memory protection. a13 157 nmi_n in nonmaskable interrupt a14 154 mp_reset in master processor reset control a15 151 not connected C C b1 3 da2 out/z d bus address 2 b2 1 da0 out/z d bus address 0 b3 198 procout C process monitor pin b4 194 int3_n in maskable interrupt #3 b5 190 int3_cntx_en in int3 automatic context switch enable b6 185 dmmc_mode in high = dmmc mode, low = normal mode b7 181 outp7 out user output 7 b8 175 outp1 out user output 1 b9 171 ext_scan_alert out scanice alert
80 CWDSP1670 lead vehicle technical summary b10 167 vdd2 in +2.5 v core power b11 164 ext_scan_ctl in scanice load control b12 159 vdd4 in +3.3 v i/o buffer power b13 153 edb_wait_en in high = enable the automatic, single wait state generation for e bus accesses b14 150 vss C ground b15 149 int3_vec15 in int3 interrupt vector address 15 c1 6 da4 out/z d bus address 4 c2 4 da3 out/z d bus address 3 c3 2 da1 out/z d bus address 1 c4 197 vss C ground c5 191 int0_n in maskable interrupt #0 c6 186 ocem_susp in suspend ocem c7 182 vdd4 in +3.3 v i/o buffer power c8 174 outp0 out user output 0 c9 170 scanice_mode out indication that scanice mode is active c10 166 ext_scan_rst in scanice reset c11 162 rst_n in reset input c12 156 escan_en in reserved, tie to vss c13 152 mp_boot in master processor boot control c14 148 int3_vec14 in int3 interrupt vector address 14 c15 146 int3_vec12 in int3 interrupt vector address 12 d1 10 vss C ground d2 7 da6 out/z d bus address 6 d3 5 da5 out/z d bus address 5 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
CWDSP1670 lead vehicle technical summary 81 d4 196 clkout_en in high = enable oak_clk, clk_ug, and timer_clk outputs d5 193 int2_n in maskable interrupt #2 d6 187 vdd2 in +2.5 v core power d7 183 vss C ground d8 177 outp3 out user output 3 d9 173 vss C ground d10 163 ext_scan_in in scanice data in d11 158 level_int_mode in high = level-triggered interrupt mode, low = edge-triggered interrupt mode d12 155 escan_in in reserved, tie to vss d13 147 int3_vec13 in int3 interrupt vector address 13 d14 145 int3_vec11 in int3 interrupt vector address 11 d15 142 int3_vec8 in int3 interrupt vector 8 e1 14 da10 out/z d bus address 10 e2 12 da9 out/z d bus address 9 e3 9 vdd4 in +3.3 v i/o buffer power e4 8 da8 out/z d bus address 8 e5 11 da7 out/z d bus address 7 e6 189 im3 in int3 mask control e7 179 outp5 out user output 5 e8 178 outp4 out user output 4 e9 169 ext_scan_out out scanice data out e10 160 vss C ground e11 141 vss C ground e12 144 int3_vec10 in int3 interrupt vector address 10 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
82 CWDSP1670 lead vehicle technical summary e13 143 int3_vec9 in int3 interrupt vector address 9 e14 140 vdd4 in +3.3 v i/o buffer power e15 138 int3_vec6 in int3 interrupt vector 6 f1 18 da15 out/z d bus address 15 f2 17 da14 out/z d bus address 14 f3 16 da13 out/z d bus address 13 f4 15 da12 out/z d bus address 12 f5 13 da11 out/z d bus address 11 f6 C vdd2 in +2.5 v ram/lv logic f7 C vdd2 in +2.5 v ram/lv logic f8 C vss C ground f9 C vdd2 in +2.5 v ram/lv logic f10 C vdd2 in +2.5 v ram/lv logic f11 139 int3_vec7 in int3 interrupt vector address 7 f12 137 int3_vec5 in int3 interrupt vector address 5 f13 136 int3_vec4 in int3 interrupt vector address 4 f14 135 int3_vec3 in int3 interrupt vector address 3 f15 134 int3_vec2 in int3 interrupt vector address 2 g1 22 dd2 inout/z d bus data 2 g2 23 dd1 inout/z d bus data 1 g3 20 vss C ground g4 19 vdd4 in +3.3 v i/o buffer power g5 21 dd0 inout/z d bus data bus g6 C vdd2 in +2.5 v ram/lv logic g7 C vss C ground table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
CWDSP1670 lead vehicle technical summary 83 g8 C vss C ground g9 C vss C ground g10 C vdd2 in +2.5 v ram/lv logic g11 131 vss C ground g12 133 int3_vec1 in int3 interrupt vector address 1 g13 132 int3_vec0 in int3 interrupt vector address 0 g14 129 iack_nmi_n out nmi acknowledge g15 130 vdd4 in +3.3 v i/o buffer power h1 26 dd7 inout/z d bus data 7 h2 28 dd6 inout/z d bus data 6 h3 27 dd5 inout/z d bus data 5 h4 25 dd4 inout/z d bus data 4 h5 24 dd3 inout/z d bus data 3 h6 C vss C ground h7 C vss C ground h8 C vss C ground h9 C vss C ground h10 C vss C ground h11 128 iack_int3_n out int3 acknowledge h12 127 iack_int2_n out int2 acknowledge h13 125 iack_int0_n out int0 acknowledge h14 124 sel_xr_rd1 out external register read select 1 h15 126 iack_int1_n out int1 acknowledge j1 30 vss C ground j2 32 dd10 inout/z d bus data 10 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
84 CWDSP1670 lead vehicle technical summary j3 31 dd9 inout/z d bus data 9 j4 29 vdd4 in +3.3 v i/o buffer power j5 33 dd8 inout/z d bus data 8 j6 C vdd2 in +2.5 v ram/lv logic j7 C vss C ground j8 C vss C ground j9 C vss C ground j10 C vdd2 in +2.5 v ram/lv logic j11 119 xrw2_n out write enable for ext. reg. #2 j12 123 sel_xr_rd0 out external register read select 0 j13 121 vdd4 in +3.3 v i/o buffer power j14 120 xrw3_n out write enable for ext. reg. #3 j15 122 vss C ground k1 34 dd14 inout/z d bus data 14 k2 36 dd13 inout/z d bus data 13 k3 35 dd12 inout/z d bus data 12 k4 37 dd11 inout/z d bus data 11 k5 39 vdd4 in +3.3 v i/o buffer power k6 C vdd2 in +2.5 v ram/lv logic k7 C vdd2 in +2.5 v ram/lv logic k8 C vss C ground k9 C vdd2 in +2.5 v ram/lv logic k10 C vdd2 in +2.5 v ram/lv logic k11 113 xrr0_n out read enable for ext. reg. #0 k12 115 xrr2_n out read enable for ext. reg. #2 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
CWDSP1670 lead vehicle technical summary 85 k13 117 xrw0_n out write enable for ext. reg. #0 k14 116 xrr3_n out read enable for ext. reg. #3 k15 118 xrw1_n out write enable for ext. reg. #1 l1 38 dd15 inout/z d bus data 15 l2 41 dw_n out/z d bus write enable l3 43 ioc_n out/z i/o chip select l4 44 dc_n out/z d bus chip select l5 40 vss C ground l6 60 emem_wait in high = 1 wait state for e memory (m4 cleared), low = zero wait states for e memory l7 70 vss C ground l8 74 xrdi11 in external register data input 11 l9 83 rst_out_n out synchronized to oak_clk version of rst_n l10 92 xrdo1 out external register data output 1 l11 112 vss C ground l12 108 xrdo13 out external register data output 13 l13 109 xrdo14 out external register data output 14 l14 111 vdd4 in +3.3 v i/o buffer power l15 114 xrr1_n out read enable for ext. reg. #1 m1 42 dr_n out/z d bus read enable m2 46 iow_n out/z i/o write enable m3 47 d_dma_n in low = external dma controller becomes d bus master m4 48 wait_ctl_n in external wait control m5 57 iu0 in user input 0 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
86 CWDSP1670 lead vehicle technical summary m6 62 xrdi1 in external register data input 1 m7 67 xrdi6 in external register data input 6 m8 75 xrdi12 in external register data input 12 m9 79 vdd4 in +3.3 v i/o buffer power m10 89 vdd4 in +3.3 v i/o buffer power m11 94 xrdo3 out external register data output 3 m12 104 xrdo9 out external register data output 9 m13 105 xrdo10 out external register data output 10 m14 106 xrdo11 out external register data output 11 m15 110 xrdo15 out external register data output 15 n1 45 ior_n out/z i/o read enable n2 50 vss C ground n3 52 tn C production test n4 56 self_test_n in self-test boot enable n5 63 xrdi2 in external register data input 2 n6 66 xrdi5 in external register data input 5 n7 71 xrdi8 in external register data input 8 n8 78 xrdi14 in external register data input 14 n9 82 stop_mode out high = CWDSP1670 core is in stop mode n10 86 brrm1 out high = brr $-1 execution n11 90 vss C ground n12 96 xrdo5 out external register data output 5 n13 100 not connected C C n14 102 xrdo7 out external register data output 7 n15 107 xrdo12 out external register data output 12 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
CWDSP1670 lead vehicle technical summary 87 p1 49 d_dma_grant out high = dma has been granted d bus. da, dd, dw_n, dr_n, dc_n, iow_n, ior_n, and ioc_n are 3-stated. p2 53 mp_abort in master processor abort control p3 55 abort_n in abort input p4 59 clk_ug out copy of CWDSP1670 core clock without wait states p5 64 xrdi3 in external register data input 3 p6 68 xrdi7 in external register data input 7 p7 72 xrdi9 in external register data input 9 p8 77 xrdi15 in external register data input 15 p9 81 abort_out out abort acknowledge p10 85 oak_clk out copy of CWDSP1670 core clock p11 88 ou0 out user output 0 p12 93 xrdo2 out external register data output 2 p13 97 vdd4 in +3.3 v i/o buffer power p14 99 ptst in production test enable p15 103 xrdo8 out external register data output 8 r1 51 not connected C C r2 54 boot_n in boot control (boot from rom when low) r3 58 iu1 in user input 1 r4 61 xrdi0 in external register data input 0 r5 65 xrdi4 in external register data input 4 r6 69 vdd4 in +3.3 v i/o buffer power r7 73 xrdi10 in external register data input 10 r8 76 xrdi13 in external register data input 13 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
88 CWDSP1670 lead vehicle technical summary r9 80 vss C ground r10 84 timer_clk out timer input clock, gated copy of mclk r11 87 ou1 out user output 1 r12 91 xrdo0 out external register data output 0 r13 95 xrdo4 out external register data output 4 r14 98 ptst_te in production test scan chain load enable r15 101 xrdo6 out external register data output 6 table 13 signal listing by ball number (cont.) solder ball bond pad signal name i/o description
CWDSP1670 lead vehicle technical summary 89 figure 27 225 pbga (ib) mechanical drawing md97.ib impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code ib.
90 CWDSP1670 lead vehicle technical summary figure 28 pin assignments seen from solder ball side abcdefghj kl mnpr 1 da[2] da[4] vss da[10] da[15] dd[2] dd[7] vss dd[14] dd[15] dr_n ior_n d_dma_ grant 2 escan_ out da[0] da[3] da[6] da[9] da[14] dd[1] dd[6] dd[10] dd[13] dw_n iow_n vss mp_abo rt boot_n 3 iiddtn pro- cout da[1] da[5] vdd4 da[13] vss dd[5] dd[9] dd[12] ioc_n d_dma_ n tn abort_ n iu1 4 int1_n int3_n vss clkout _en da[8] da[12] vdd4 dd[4] vdd4 dd[11] dc_n wait_ct l_n self_te st_n clk_ug xrdi[0] 5 vss int3_cn tx_en int0_n int2_n da[7] da[11] dd[0] dd[3] dd[8] vdd4 vss iu0 xrdi[2] xrdi[3] xrdi[4] 6 mclk dmmc_ mode ocem_s usp vdd2 im3 emem_ wait xrdi[1] xrdi[5] xrdi[7] vdd4 7 outp[6] outp[7] vdd4 vss outp[5] vss xrdi[6] xrdi[8] xrdi[9] xrdi[10] 8 outp[2] outp[1] outp[0] outp[3] outp[4] xrdi[11] xrdi[12] xrdi[14] xrdi[15] xrdi[13] 9 scan_d ebug_e n ext_sc an_ale rt scanic e_mode vss ext_sc an_out rst_ou t_n vdd4 stop_m ode abort_ out vss 10 vss vdd2 ext_sc an_rst ext_sc an_in vss xrdo[1] vdd4 brrm1 oak_cl k timer_c lk 11 ext_sc an_clk ext_sc an_ctl rst_n level_i nt_mod e vss int3_ve c[7] vss iack_in t3_n xrw2_n xrr0_n vss xrdo[3] vss ou0 ou1 12 pprote ct_en vdd4 escan_ en escan_i n int3_ve c[10] int3_ve c[5] int3_ve c[1] iack_in t2_n sel_xr_ rd[0] xrr2_n xrdo[13 ] xrdo[9] xrdo[5] xrdo[2] xrdo[0] 13 nmi_n edb_wa it_en mp_boo t int3_ve c[13] int3_ve c[9] int3_ve c[4] int3_ve c[0] iack_in t0_n vdd4 xrw0_n xrdo[14 ] xrdo[10 ] vdd4 xrdo[4] 15 mp_rst vss int3_ve c[14] int3_ve c[11] vdd4 int3_ve c[3] iack_nm i_n sel_xr_ rd[1] xrw3_n xrr3_n vdd4 xrdo[11 ] xrdo[7] ptst ptst_te 15 int3_ve c[15] int3_ve c[12] int3_ve c[8] int3_ve c[6] int3_ve c[2] vdd4 iack_in t1_n vss xrw1_n xrr1_n xrdo[15 ] xrdo[12 ] xrdo[8] xrdo[6]
CWDSP1670 lead vehicle technical summary 91 9 known limitations this section describes known bugs and limitations. 9.1 int3_vec pin the two least signi?cant bits of this port must be tied to vss. this limits the choice of possible interrupt service routine addresses for interrupt 3 to addresses that are divisable by 4.
to receive product literature, visit us at http://www.lsilogic.com. 92 CWDSP1670 lead vehicle technical summary lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or lia- bility arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. this document is preliminary. as such, it contains data derived from functional simulations and performance esti- mates. lsi logic has not veri?ed the functional descriptions or electrical and mechanical speci?cations using production parts. the lsi logic logo design, and coreware are registered trademarks of lsi logic corporation. oakdspcore and pinedspcore are registered trademarks of dsp group, inc., used under license. all other brand and product names may be trademarks of their respective companies. printed in usa order no. c15041 doc. no. db09-000092-00 headquarters lsi logic corporation north american headquarters milpitas ca tel: 408.433.8000 fax: 408.433.8989 lsi logic europe ltd european headquarters bracknell england tel: 44.1344.426544 fax: 44.1344.481039 lsi logic k.k. headquarters tokyo japan tel: 81.3.5463.7821 fax: 81.3.5463.7820 printed on recycled paper iso 9000 certified notes

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